ProASIC
PLUS
Flash Family FPGAs
Boundary Scan (JTAG)
ProASIC
PLUS
devices are compatible with IEEE Standard
1149.1, which defines a set of hardware architecture and
mechanisms for cost-effective, board-level testing. The
basic ProASIC
PLUS
boundary-scan logic circuit is composed
of the TAP (test access port), TAP controller, test data
registers, and instruction register (Figure
This circuit
supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD and BYPASS) and the optional
IDCODE instruction (Table
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI and TDO
(test data input and output), TMS (test mode selector)
and TRST (test reset input). TMS, TDI and TRST are
equipped with pull-up resistors to ensure proper
operation when no input data is supplied to them. These
pins are dedicated for boundary-scan test usage. Actel
recommends that a nominal 20 kΩ pull-up resistor is
added to TDO and TCK pins.
The TAP controller is a four-bit state machine (16 states)
that operates as shown in
The
1s and 0s represent the values that must be present at
TMS at a rising edge of TCK for the given state transition
to occur. IR and DR indicate that the instruction register
or the data register is operating in that state.
ProASIC
PLUS
devices have to be programmed at least
once for complete boundary-scan functionality to be
available. Prior to being programmed, EXTEST is not
available. If boundary-scan functionality is required prior
to programming, refer to online
on the
Actel website and search for ProASIC
PLUS
BSDL.
I/O
I/O
I/O
I/O
I/O
Test Data
Registers
TDI
TCK
TMS
TAP
Controller
Instruction
Register
Device
Logic
TRST
TDO
I/O
I/O
I/O
I/O
I/O
Figure 2-9 •
ProASIC
PLUS
JTAG Boundary Scan Test Logic Circuit
Table 2-6 •
Boundary-Scan Opcodes
Hex Opcode
EXTEST
SAMPLE/PRELOAD
IDCODE
00
01
0F
CLAMP
BYPASS
Table 2-6 •
Boundary-Scan Opcodes
Hex Opcode
05
FF
2 -8
v5.9
I/O
I/O
I/O
I/O
Bypass Register
ACTEL [ Actel Corporation ]
