ProASIC
PLUS
Flash Family FPGAs
Operating Conditions
and
delineate operating limits.
Table 2-17 •
Absolute Maximum Ratings*
Parameter
Supply Voltage Core (V
DD
)
Supply Voltage I/O Ring (V
DDP
)
DC Input Voltage
PCI DC Input Voltage
PCI DC Input Clamp Current (absolute)
LVPECL Input Voltage
GND
V
IN
< –1 or V
IN
= V
DDP
+ 1 V
Condition
Minimum
–0.3
–0.3
–0.3
–1.0
10
–0.3
0
V
DDP
+ 0.5
0
Maximum
3.0
4.0
V
DDP
+ 0.3
V
DDP
+ 1.0
Units
V
V
V
V
mA
V
V
Note:
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the
Recommended Operating Conditions.
Table 2-18 •
Programming, Storage, and Operating Limits
Storage Temperature
Operating
T
J
Max.
Junction
Temperature
110°C
110°C
150°C
150°C
Product Grade
Commercial
Industrial
Military
MIL-STD-883
Programming Cycles (min.)
500
500
100
100
Program Retention (min.)
20 years
20 years
Refer to
Refer to
Min.
–55°C
–55°C
–65°C
–65°C
Max.
110°C
110°C
150°C
150°C
Performance Retention
For devices operated and stored at 110°C or less, the
performance retention period is 20 years after
programming. For devices operated and stored at
temperatures greater than 110°C, refer to
to determine the performance retention
period. Actel does not guarantee performance if the
performance retention period is exceeded. Designers can
determine the performance retention period from the
following table.
Evaluate the percentage of time spent at the highest
temperature, then determine the next highest
temperature to which the device will be exposed. In
find the temperature profile
that most closely matches the application.
Example – the ambient temperature of a system cycles
between 100°C (25% of the time) and 50°C (75% of the
time). No forced ventilation cooling system is in use. An
APA600-PQ208M FPGA operates in the system,
dissipating 1 W. The package thermal resistance
(junction-to-ambient) in still air
Θ
ja
is 20°C/W, indicating
that the junction temperature of the FPGA will be 120°C
(25% of the time) and 70°C (75% of the time). The entry
in
which most closely matches
the application, is 25% at 125°C with 75% at 110°C.
Performance retention in this example is at least 16.0
years.
Note that exceeding the stated retention period may
result in a performance degradation in the FPGA below
the worst-case performance indicated in the Actel Timer.
To ensure that performance does not degrade below the
worst-case values in the Actel Timer, the FPGA must be
reprogrammed within the performance retention
period. In addition, note that performance retention is
independent of whether or not the FPGA is operating.
The retention period of a device in storage at a given
temperature will be the same as the retention period of
a device operating at that junction temperature.
v5.9
2-31
ACTEL [ Actel Corporation ]
