ProASIC
PLUS
Flash Family FPGAs
Tristate Buffer Delays
EN
A
OTBx
A
PAD
V
OL
t
DLH
50% 50%
V
OH
50%
t
DHL
50%
50% 50%
V
DDP
50%
PAD
V
OL
t
ENZL
EN
PAD
35 pF
EN
10%
PAD
GND
t
ENZH
50% 50%
V
OH
50%
90%
Figure 2-23 •
Tristate Buffer Delays
Table 2-27 •
Worst-Case Commercial Conditions
V
DDP
= 3.0 V, V
DD
= 2.3 V, 35 pF load, T
J
= 70°C
Max.
t
DLH1
Macro Type
OTB33PH
OTB33PN
OTB33PL
OTB33LH
OTB33LN
OTB33LL
Notes:
1.
2.
3.
4.
t
DLH
= Data-to-Pad High
t
DHL
= Data-to-Pad Low
t
ENZH
= Enable-to-Pad, Z to High
t
ENZL
= Enable-to-Pad, Z to Low
Description
3.3 V, PCI Output Current, High Slew Rate
3.3 V, High Output Current, Nominal Slew Rate
3.3 V, High Output Current, Low Slew Rate
3.3 V, Low Output Current, High Slew Rate
3.3 V, Low Output Current, Nominal Slew Rate
3.3 V, Low Output Current, Low Slew Rate
Std.
2.0
2.2
2.5
2.6
2.9
3.0
Max.
t
DHL2
Std.
2.2
2.9
3.2
4.0
4.3
5.6
Max. Max.
t
ENZH3
t
ENZL4
Std.
2.2
2.4
2.7
2.8
3.2
3.3
Std.
2.0
2.1
2.8
3.0
4.1
5.5
Units
ns
ns
ns
ns
ns
ns
Table 2-28 •
Worst-Case Commercial Conditions
V
DDP
= 2.3 V, V
DD
= 2.3 V, 35 pF load, T
J
= 70°C
Max.
t
DLH1
Macro Type
OTB25LPHH
OTB25LPHN
OTB25LPHL
OTB25LPLH
OTB25LPLN
OTB25LPLL
Notes:
1.
2.
3.
4.
5.
t
DLH
= Data-to-Pad High
t
DHL
= Data-to-Pad Low
t
ENZH
= Enable-to-Pad, Z to High
t
ENZL
= Enable-to-Pad, Z to Low
Low power I/O work with V
DDP
= 2.5 V ±10% only. V
DDP
= 2.3 V for delays.
Description
2.5 V, Low Power, High Output Current, High Slew Rate
5
2.5 V, Low Power, High Output Current, Nominal Slew Rate
5
2.5 V, Low Power, High Output Current, Low Slew Rate
5
2.5 V, Low Power, Low Output Current, High Slew Rate
5
2.5 V, Low Power, Low Output Current, Nominal Slew Rate
5
2.5 V, Low Power, Low Output Current, Low Slew Rate
5
Std.
2.0
2.4
2.9
2.7
3.5
4.0
Max.
t
DHL2
Std.
2.1
3.0
3.2
4.6
4.2
5.3
Max.
t
ENZH3
Std.
2.3
2.7
3.1
3.0
3.8
4.2
Max.
t
ENZL4
Std.
2.0
2.1
2.7
2.6
3.8
5.1
Units
ns
ns
ns
ns
ns
ns
2 -4 2
v5.9
ACTEL [ Actel Corporation ]
