ProASIC
PLUS
Flash Family FPGAs
Global Input Buffer Delays
Table 2-39 •
Worst-Case Commercial Conditions
V
DDP
= 3.0 V, V
DD
= 2.3 V, T
J
= 70°C
Max. t
INYH1
Macro Type
GL33
GL33S
PECL
Notes:
1.
2.
3.
4.
5.
t
INYH
= Input Pad-to-Y High
t
INYL
= Input Pad-to-Y Low
Applies to Military ProASIC
PLUS
devices.
LVTTL delays are the same as CMOS delays.
For LP Macros, V
DDP
= 2.3 V for delays.
Description
3.3 V, CMOS Input Levels
4
, No Pull-up Resistor
3.3 V, CMOS Input Levels
4
, No Pull-up Resistor, Schmitt Trigger
PPECL Input Levels
Std.
3
1.0
1.0
1.0
Max. t
INYL2
Std.
3
1.1
1.1
1.1
ns
ns
ns
Units
Table 2-40 •
Worst-Case Commercial Conditions
V
DDP
= 2.3 V, V
DD
= 2.3 V, T
J
= 70°C
Max. t
INYH1
Macro Type
GL25LP
GL25LPS
Notes:
1.
2.
3.
4.
5.
t
INYH
= Input Pad-to-Y High
t
INYL
= Input Pad-to-Y Low
Applies to Military ProASIC
PLUS
devices.
LVTTL delays are the same as CMOS delays.
For LP Macros, V
DDP
= 2.3 V for delays.
Description
2.5 V, CMOS Input Levels
4
, Low Power
2.5 V, CMOS Input Levels
4
, Low Power, Schmitt Trigger
Std.
3
1.1
1.3
Max. t
INYL2
Std.
3
1.0
1.0
ns
ns
Units
2 -4 8
v5.9
ACTEL [ Actel Corporation ]
