ProASIC
PLUS
Flash Family FPGAs
ProASIC
PLUS
Architecture
The proprietary ProASIC
PLUS
architecture
granularity comparable to gate arrays.
provides
The ProASIC
PLUS
device core consists of a Sea-of-Tiles
Each tile can be configured as a three-input
logic function (e.g., NAND gate, D-Flip-Flop, etc.) by
programming
the
appropriate
flash
switch
interconnections (Figure
and
Tiles and larger functions are connected with any of the
four levels of routing hierarchy. Flash switches are
distributed throughout the device to provide
nonvolatile, reconfigurable interconnect programming.
Flash switches are programmed to connect signal lines to
the appropriate logic cell inputs and outputs. Dedicated
high-performance lines are connected as needed for fast,
low-skew global signal distribution throughout the core.
Maximum core utilization is possible for virtually any
design.
ProASIC
PLUS
devices also contain embedded, two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming
options
include
synchronous
or
asynchronous operation, two-port RAM configurations,
user-defined depth and width, and parity generation or
checking.
Refer
to
the
for more
information.
RAM Block
256x9 Two-Port SRAM
or FIFO Block
I/Os
Logic Tile
RAM Block
256x9 Two Port SRAM
or FIFO Block
Figure 1-1 •
The ProASIC
PLUS
Device Architecture
Floating Gate
Switch In
Sensing
Switching
Word
Switch Out
Figure 1-2 •
Flash Switch
1 -2
v5.9
ACTEL [ Actel Corporation ]
