Axcelerator Family FPGAs
I/O Specifications
Pin Descriptions
Supply Pins
GND
Ground
Axcelerator Chip
250
Ω
1.5V Supply
10µf
0.1µf
V
COMPLX
V
CCPLX
Low supply voltage.
V
CCA
Supply Voltage
Supply voltage for array (1.5V). See
for more information.
V
CCIBx
Supply Voltage
Figure 2-2 •
V
CCPLX
and V
COMPLX
Power Supply Connect
Supply voltage for I/Os. Bx is the I/O Bank ID – 0 to 7. See
for more
information.
V
CCDA
Supply Voltage
User-Defined Supply Pins
V
REF
Supply Voltage
Supply voltage for the I/O differential amplifier and JTAG
and probe interfaces. See
for more information. V
CCDA
should be tied to
3.3V.
V
CCPLA/B/C/D/E/F/G/H
Supply Voltage
Reference voltage for I/O banks. V
REF
pins are configured
by the user from regular I/O pins; V
REF
pins are not in
fixed locations. There can be one or more V
REF
pins in an
I/O bank.
Global Pins
HCLKA/B/C/D
Dedicated (Hardwired) Clocks A, B, C
and D
PLL analog power supply (1.5V) for internal PLL. There
are eight in each device. V
CCPLA
supports the PLL
associated with global resource HCLKA, V
CCPLB
supports
the PLL associated with global resource HCLKB, etc. The
PLL analog power supply pins should be connected to
1.5V whether PLL is used or not.
V
COMPLA/B/C/D/E/F/G/H
Supply Voltage
Compensation reference signals for internal PLL. There
are eight in each device. V
COMPLA
supports the PLL
associated with global resource HCLKA, V
COMPLE
supports the PLL associated with global resource CLKE,
etc. (see
for correct external
connection to the supply). The V
COMPLX
pins should be
left floating if PLL is not used.
V
PUMP
Supply Voltage (External Pump)
These pins are the clock inputs for sequential modules or
north PLLs. Input levels are compatible with all
supported I/O standards. There is a P/N pin pair for
support of differential I/O standards. Single-ended clock
I/Os can only be assigned to the P side of a paired I/O.
This input is directly wired to each R-cell and offers clock
speeds independent of the number of R-cells being
driven. When the HCLK pins are unused, it is
recommended that they are tied to ground.
CLKE/F/G/H
Routed Clocks E, F, G, and H
In the low power mode, V
PUMP
will be used to access an
external charge pump (if the user desires to bypass the
internal charge pump to further reduce power). The
device starts using the external charge pump when the
voltage level on V
PUMP
reaches V
IH1
. In normal device
operation, when using the internal charge pump, V
PUMP
should be tied to GND.
These pins are clock inputs for clock distribution
networks or south PLLs. Input levels are compatible with
all supported I/O standards. There is a P/N pin pair for
support of differential I/O standards. Single-ended clock
I/Os can only be assigned to the P side of a paired I/O.
The clock input is buffered prior to clocking the R-cells.
When the CLK pins are unused, Actel recommends that
they are tied to ground.
1. When V
PUMP
= V
IH
, it shuts off the internal charge pump. See
v2.7
2-9
ACTEL [ Actel Corporation ]
