AX2000-FGG896 参数 Datasheet PDF下载

型号：	AX2000-FGG896
PDF下载：	下载PDF文件查看货源
内容描述：	的Axcelerator系列FPGA [Axcelerator Family FPGAs]
分类和应用：
文件页数/大小：	226 页 / 2293 K
品牌：	ACTEL [ Actel Corporation ]

Axcelerator Family FPGAs

SuperCluster

RAMC

RAM/

FIFO

RAM/

FIFO

RAMC

Chip Layout

RAM/

FIFO

RAM/

FIFO

Core

Tile

I/O Structure

See Figure 7

Figure 1-6 •

AX Device Architecture (AX1000 shown)

Embedded Memory

As mentioned earlier, each core tile has either three (in a

smaller tile) or four (in the regular tile) embedded SRAM

blocks along the west side, and each variable-aspect-

ratio SRAM block is 4,608 bits in size. Available memory

configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or

4kx1 bits. The individual blocks have separate read and

write ports that can be configured with different bit

widths on each port. For example, data can be written in

by eight and read out by one.

In addition, every SRAM block has an embedded FIFO

control unit. The control unit allows the SRAM block to

be configured as a synchronous FIFO without using core

logic modules. The FIFO width and depth are

programmable. The FIFO also features programmable

ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL)

flags in addition to the normal EMPTY and FULL flags. In

addition to the flag logic, the embedded FIFO control

unit also contains the counters necessary for the

generation of the read and write address pointers as well

as control circuitry to prevent metastability and

erroneous operation. The embedded SRAM/FIFO blocks

can be cascaded to create larger configurations.

I/O Logic

The Axcelerator family of FPGAs features a flexible I/O

structure, supporting a range of mixed voltages with its

bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V. In all,

Axcelerator FPGAs support at least 14 different I/O

standards (single-ended, differential, voltage-referenced).

The I/Os are organized into banks, with eight banks per

device (two per side). The configuration of these banks

determines the I/O standards supported (see

"User I/Os"

on page 2-10

for more information). All I/O standards are

available in each bank.

Each I/O module has an input register (InReg), an output

(Figure

1-7 on page 1-5).

An I/O Cluster includes two I/O

modules, four RX modules, two TX modules, and a buffer

(B) module.

1 -4

v2.7

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