eX Automotive Family FPGAs
Other Architectural Features
Performance
The combination of the various architectural features
enables automotive-grade eX devices to operate with
internal clock frequencies at 250 MHz for fast execution
of complex logic functions.
Automotive-grade eX devices are the optimal platforms
upon which to integrate in-cabin telematics and
automobile interconnect applications previously only
contained in ASICs or gate arrays.
eX devices meet the performance goals of gate arrays,
and, at the same time, present significant improvements
in cost and time to market. Using timing-driven place-
and-route tools, designers can achieve highly
deterministic device performance.
to GND on the board. Each I/O module has an available
pull-up or pull-down resistor of approximately 50 kΩ
that can configure the I/O in a known state during
power-up. Just shortly before V
CCA
reaches 2.5 V, the
resistors are disabled and the I/Os will be controlled by
user logic.
describes the I/O features of eX devices. For
more information on I/Os, refer to the
application note.
The automotive eX devices support I/O operation at 2.5 V
and 3.3 V.
The detailed description of the I/O pins in eX automotive
devices can be found in
Table 1-2 •
I/O Features
Function
Description
3.3 V LVTTL
2.5 V LVCMOS2
3.3 V LVTTL
2.5 V LVCMO 2
I/O on an unpowered device does not sink
current
Can be used for “cold sparing”
Selectable on an individual I/O basis
Input Buffer •
Threshold
•
Selection
Nominal
Output Drive
•
•
•
•
•
Power-Up
User Security
The Actel FuseLock advantage ensures that unauthorized
users will not be able to read back the contents of an
Actel antifuse FPGA. In addition to the inherent
strengths of the architecture, there is a special Security
Fuse inside the eX device that disables the probing
circuitry and prohibits further programming of the
device. This Fuse cannot be accessed or bypassed without
destroying access to the rest of the device, making both
invasive and more-subtle noninvasive attacks ineffective
against Actel antifuse FPGAs.
Look for this symbol to ensure your valuable IP is secure.
Output Buffer “Hot-Swap” Capability
Individually selectable low-slew option
Individually selectable pull-ups and pull-downs
during power-up (default is to power-up in
tristate)
Enables deterministic power-up of device
V
CCA
and V
CCI
can be powered in any order
FuseLock
Figure 1-7 •
FuseLock
Hot Swapping
eX I/Os are configured to be hot-swappable. During
power-up/down (or partial up/down), all I/Os are tristated,
provided V
CCA
ramps up within a diode drop of V
CCI
. V
CCA
and V
CCI
do not have to be stable during power-up/down,
and they do not require a specific power-up or power-
down sequence in order to avoid damage to the eX
devices. In addition, all outputs can be programmed to
have a weak resistor pull-up or pull-down for tristate
output at power-up. After the eX device is plugged into
an electrically active system, the device will not degrade
the reliability of or cause damage to the host system. The
device's output pins are driven to a high impedance state
until normal chip operating conditions are reached. Please
see the application note,
which also
applies to eX devices, for more information on hot
swapping.
For more information, refer to Actel's
application note.
I/O Modules
Each I/O on an eX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. I/O cells in
eX devices do not contain embedded latches or flip-flops
and can be inferred directly from HDL code. The device
can easily interface with any other device in the system,
which in turn enables parallel design of system
components and reduces overall design time.
All unused I/Os are configured as tristate outputs by
Actel's Designer software, for maximum flexibility when
designing new boards or migrating existing designs.
However, it is still recommended to tie all unused I/O pins
v3.2
1-5
ACTEL [ Actel Corporation ]
