IGLOOe Device Family Overview
The FlashROM can be programmed via the JTAG programming interface, and its contents can be
read back either through the JTAG programming interface or via direct FPGA core addressing. Note
that the FlashROM can only be programmed from the JTAG interface and cannot be programmed
from the internal logic array.
The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-
byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8
banks and which of the 16 bytes within that bank are being read. The three most significant bits
(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of
the FlashROM address define the byte.
The Actel IGLOOe development software solutions, Libero
®
Integrated Design Environment (IDE)
and Designer, have extensive support for the FlashROM. One such feature is auto-generation of
sequential programming files for applications requiring a unique serial number in each part.
Another feature allows the inclusion of static data for system version control. Data for the
FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.
Comprehensive programming file support is also included to allow for easy programming of large
numbers of parts with differing FlashROM contents.
SRAM and FIFO
IGLOOe devices have embedded SRAM blocks along their north and south sides. Each variable-
aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,
1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be
configured with different bit widths on each port. For example, data can be sent through a 4-bit
port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device
JTAG port (ROM emulation mode) using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the
SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The
FIFO width and depth are programmable. The FIFO also features programmable Almost Empty
(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The
embedded FIFO control unit contains the counters necessary for generation of the read and write
address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOOe devices provide designers with very flexible clock conditioning capabilities. Each member
of the IGLOOe family contains six CCCs, each with an integrated PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One
CCC (center west side) has a PLL.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
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Wide input frequency range (f
IN_CCC
) = 1.5 MHz up to 250 MHz
Output frequency range (f
OUT_CCC
) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output
divider configuration.
Output duty cycle = 50% ± 1.5% or better
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single
global network used
Maximum acquisition time is 300 µs
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
f
OUT_CCC
Additional CCC specifications:
1 -6
v1.2
ACTEL [ Actel Corporation ]
