IGLOOe Low-Power Flash FPGAs
Global Clocking
IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three
quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the
core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for
rapid distribution of high-fanout nets.
Pro I/Os with Advanced I/O Standards
The IGLOOe family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V,
1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOOe FPGAs support 19 different I/O standards, including single-
ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks
per device (two per side). The configuration of these banks determines the I/O standards
supported. Each I/O bank is subdivided into V
REF
minibanks, which are used by voltage-referenced
I/Os. V
REF
minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common V
REF
line.
Therefore, if any I/O in a given V
REF
minibank is configured as a V
REF
pin, the remaining I/Os in that
minibank will be able to use that reference voltage.
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
•
Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).
IGLOOe banks support M-LVDS with 20 multi-drop points.
v1.2
1-7
ACTEL [ Actel Corporation ]
