ACT8600
Rev 3, 15-Nov-12
REGISTER AND BIT DESCRIPTIONS CONT’D
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Input Voltage Interrupt Control. Set both this bit and
INSTAT[ ] to 1 to generate an interrupt when CHGIN input
voltage goes out of the valid range. See the Charge Current
Programming section for more information.
APCH
APCH
0xA9
0xA9
[1]
INDIS
R/W
Charge State Interrupt Control. Set both this bit and
CHGSTAT[ ] to 1 to generate an interrupt when the state
machines jumps out of the EOC state. See the State Machine
Interrupts section for more information.
[0] CHGEOCOUT
R/W
Charge source indicator. Value is 1 when charging from AC
source and value is 0 when charging from other source.
APCH
APCH
0xAA
0xAA
[7]
[6]
CHG_ACIN
CHG_USB
R
R
Charge source indicator. Value is 1 when charging from USB
source and value is 0 when charging from other source.
Charge State. Values indicate the current charging state. See
the State Machine Interrupts section for more information.
APCH
APCH
APCH
0xAA
0xAA
0xAA
[5:4]
[3:1]
CSTATE
-
R
R
R
Reserved.
CHGLEV pin status. Value is 0 if CHGLEVSTAT is logic low;
value is 1 otherwise.
[0] CHGLEVSTAT
OTG Q1 Enable Bit. Set bit to 1 to turn on Q1; clear bit to 0 to
turn off Q1.
OTG
OTG
OTG
OTG
OTG
0xB0
0xB0
0xB0
0xB0
0xB0
[7]
[6]
[5]
[4]
[3]
ONQ1
ONQ2
ONQ3
Q1OK
Q2OK
R/W
R/W
R/W
R
OTG Q2 Enable Bit. Set bit to 1 to turn on Q2; clear bit to 0 to
turn off Q2.
OTG Q3 Enable Bit. Set bit to 1 to turn on Q3; clear bit to 0 to
turn off Q3.
OTG Q1 Status. Value is 0 if Q1 can not start up successfully,
or in current limit status.
OTG Q2 Status. Value is 0 if Q2 can not start up successfully,
or in current limit status.
R
VBUS Interrupt Status. Value is 1 if an interrupt is generated
by either INVBUSR or INVBUSF.
OTG
OTG
OTG
0xB0
0xB0
0xB0
[2]
[1]
[0]
VBUSSTAT
DBILIMQ3
VBUSDAT
R
R/W Set to 1 to double the current limit of Q3.
VBUS status. Value is 1 if a valid charging source is present at
VBUS. Value is 0 otherwise.
R
VBUS Interrupt control. Set this bit to 1 to generate an
R/W interrupt when connecting a charger to VBUS (rising edge of
VBUS).
OTG
OTG
0xB2
0xB2
[7]
[6]
INVBUSR
INVBUSF
VBUS Interrupt control. Set this bit to 1 to generate an
R/W interrupt when disconnecting a charger to VBUS (falling edge
of VBUS).
OTG
OTG
0xB2
0xB2
[5:4]
[3]
-
R
Reserved.
Q1 Interrupt Mask. Set this bit to 1 to generate an interrupt
when the over-current threshold for Q1 is triggered.
nFLTMSKQ1
R/W
Q2 Interrupt Mask. Set this bit to 1 to generate an interrupt
when the over-current threshold for Q2 is triggered.
OTG
0xB2
[2]
nFLTMSKQ2
R/W
VBUS Interrupt Mask. Set this bit to 1 unmask to VBUS
connection and/or disconnection interrupt.
OTG
OTG
INT
0xB2
0xB2
0xC1
[1]
[0]
nVBUSMSK
R/W
R
-
Reserved.
Global Interrupt Address. See the Interrupt Service Routine
Section for more information.
[ 7:0 ]
INTADR
R
c: Valid only when CHGIN UVLO Threshold<VCHGIN<CHGIN OVP Threshold.
Innovative PowerTM
- 15 -
www.active-semi.com
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.
I2CTM is a trademark of NXP.
Copyright © 2012 Active-Semi, Inc.
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
