ADM1485–SPECIFICATIONS
(V
Parameter
DRIVER
Differential Output Voltage, V
OD
V
OD3
Δ|V
OD
| for Complementary Output States
Common-Mode Output Voltage V
OC
Δ|V
OD
| for Complementary Output States
Output Short-Circuit Current (V
OUT
= High)
Output Short-Circuit Current (V
OUT
= Low)
CMOS Input Logic Threshold Low, V
INL
CMOS Input Logic Threshold High, V
INH
Logic Input Current (DE, DI)
RECEIVER
Differential Input Threshold Voltage, V
TH
Input Voltage Hysteresis,
ΔV
TH
Input Resistance
Input Current (A, B)
CMOS Input Logic Threshold Low, V
INL
CMOS Input Logic Threshold High, V
INH
Logic Enable Input Current (RE)
CMOS Output Voltage Low, V
OL
CMOS Output Voltage High, V
OH
Short-Circuit Output Current
Three-State Output Leakage Current
POWER SUPPLY CURRENT
I
CC
(Outputs Enabled)
I
CC
(Outputs Disabled)
Specifications subject to change without notice.
CC
=5V
5%. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
Unit Test Conditions/Comments
V
V
V
V
V
V
V
mA
mA
V
V
μA
V
mV
kΩ
mA
mA
V
V
μA
V
V
mA
μA
mA
mA
R =
∞,
Test Circuit 1
V
CC
= 5 V, R = 50
Ω
(RS-422), Test Circuit 1
R = 27
Ω
(RS-485), Test Circuit 1
V
TST
= –7 V to +12 V, Test Circuit 2
R = 27
Ω
or 50
Ω,
Test Circuit 1
R = 27
Ω
or 50
Ω,
Test Circuit 1
R = 27
Ω
or 50
Ω
–7 V
≤
V
O
≤
+12 V
–7 V
≤
V
O
≤
+12 V
Min
Typ
Max
5.0
5.0
5.0
5.0
0.2
3
0.2
250
250
0.8
±
1.0
2.0
1.5
1.5
35
35
2.0
–0.2
70
12
+0.2
1
–0.8
0.8
2.0
±
1
0.4
4.0
7
85
±
1.0
1.0
0.6
2.2
1
–7 V
≤
V
CM
≤
+12 V
V
CM
= 0 V
–7 V
≤
V
CM
≤
+12 V
V
IN
= +12 V
V
IN
= –7 V
I
OUT
= +4.0 mA
I
OUT
= –4.0 mA
V
OUT
= GND or V
CC
0.4 V
≤
V
OUT
≤
2.4 V
Digital Inputs = GND or V
CC
Digital Inputs = GND or V
CC
TIMING SPECIFICATIONS
(V
Parameter
CC
=5V
5%. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
Min
2
Typ
10
1
8
10
10
0
0
Max
15
5
15
25
25
2
2
Unit Test Conditions/Comments
ns
ns
ns
ns
ns
ns
ns
R
LDIFF
= 54
Ω,
C
L1
= C
L2
= 100 pF, Test Circuit 3
R
LDIFF
= 54
Ω,
C
L1
= C
L2
= 100 pF, Test Circuit 3
R
LDIFF
= 54
Ω,
C
L1
= C
L2
= 100 pF, Test Circuit 3
R
L
= 110
Ω,
C
L
= 50 pF, Test Circuit 4
R
L
= 110
Ω,
C
L
= 50 pF, Test Circuit 4
R
L
= 110
Ω,
C
L
= 50 pF, Test Circuit 4*
R
L
= 110
Ω,
C
L
= 50 pF, Test Circuit 4*
DRIVER
Propagation Delay Input to Output t
PLH
, t
PHL
Driver O/P to
O/P
t
SKEW
Driver Rise/Fall Time t
R
, t
F
Driver Enable to Output Valid
Driver Disable Timing
Matched Enable Switching
|t
AZH
–t
BZL
|, |t
BZH
–t
AZL
|
Matched Disable Switching
|t
AHZ
–t
BLZ
|, |t
BHZ
–t
ALZ
|
RECEIVER
Propagation Delay Input to Output t
PLH
, t
PHL
Skew |t
PLH
–t
PHL
|
Receiver Enable t
EN1
Receiver Disable t
EN2
Tx Pulse Width Distortion
Rx Pulse Width Distortion
*Guaranteed
by characterization.
Specifications subject to change without notice.
8
15
5
5
1
1
30
5
20
20
ns
ns
ns
ns
ns
ns
C
L
= 15 pF, Test Circuit 5
C
L
= 15 pF, Test Circuit 5
C
L
= 15 pF, R
L
= 1 kΩ, Test Circuit 6
C
L
= 15 pF, R
L
= 1 kΩ, Test Circuit 6
–2–
REV.
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