ADSP-2189M
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Clock Signals
The ADSP-2189M can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual,
Third Edition for detailed
information on this power-down feature.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2189M uses an input clock with a frequency equal
to half the instruction rate; a 37.50 MHz input clock yields a
13.3 ns processor cycle (which is equivalent to 75 MHz). Nor-
mally, instructions are executed in a single processor cycle. All
device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled.
Because the ADSP-2189M includes an on-chip oscillator cir-
cuit, an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two capaci-
tors connected as shown in Figure 3. Capacitor values are de-
pendent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
Figure 2 shows typical basic system configurations with the
ADSP-2189M, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories (mode
selectable). Programmable Wait-State generation allows the
processor connects easily to slow peripheral devices. The
ADSP-2189M also provides four external interrupts and two
serial ports or six external interrupts and one serial port. Host
Memory Mode allows access to the full external data bus, but
limits addressing to a single address bit (A0). Additional system
peripherals can be added in this mode through the use of exter-
nal hardware to generate and latch address signals.
FULL MEMORY MODE
ADSP-2189M
1/2x CLOCK
OR
CRYSTAL
CLKIN
XTAL
FL0-2
DATA23-0
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
BMS
WR
RD
ADDR13-0
14
A
13-0
D
23-16
A0-A21
24
D
15-8
DATA
CS
A
10-0
ADDR
D
23-8
DATA
BYTE
MEMORY
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
IOMS
A
13-0
CS
ADDR
D
23-0
DATA
SPORT1
SERIAL
DEVICE
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
DR1 OR FI
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
SPORT0
SERIAL
DEVICE
SCLK0
RFS0
TFS0
DT0
DR0
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
CLKIN
XTAL
CLKOUT
HOST MEMORY MODE
DSP
1
ADSP-2189M
1/2x CLOCK
OR
CRYSTAL
CLKIN
XTAL
FL0-2
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE B/PF1
MODE A/PF0
16
DATA23-8
BMS
WR
RD
A0
Figure 3. External Crystal Connections
Reset
SPORT1
SERIAL
DEVICE
SCLK1
RFS1 OR
IRQ0
TFS1 OR
IRQ1
DT1 OR FO
DR1 OR FI
IOMS
The
RESET
signal initiates a master reset of the ADSP-2189M.
The
RESET
signal must be asserted during the power-up se-
quence to assure proper initialization.
RESET
during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET
is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is ap-
plied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the
RESET
signal should be held low. On
any subsequent resets, the
RESET
signal must meet the mini-
mum pulsewidth specification, t
RSP
.
The
RESET
input contains some hysteresis; however, if you use
an RC circuit to generate your
RESET
signal, the use of an
external Schmidt trigger is recommended.
SPORT0
SERIAL
DEVICE
SCLK0
RFS0
TFS0
DT0
DR0
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
IDMA PORT
SYSTEM
INTERFACE
OR
CONTROLLER
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0
16
Figure 2. ADSP-2189M Basic System Interface
–6–
REV. A
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