ADSP-2189M
Data Memory,
Host Mode
allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).
Table IV. DMOVLAY Bits
I/O Space (Full Memory Mode)
PMOVLAY
0, 4, 5, 6, 7
1
Memory
Internal
External
Overlay 1
External
Overlay 2
A13
A12:0
2
Not Applicable Not Applicable
0
13 LSBs of Address
Between 0x2000
and 0x3FFF
1
13 LSBs of Address
Between 0x2000
and 0x3FFF
The ADSP-2189M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit-wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait-state
registers, IOWAIT0–3, which, in combination with the wait-
state mode bit, specify up to 15 wait-states to be automatically
generated for each of four regions. The wait-states act on ad-
dress ranges as shown in Table V.
Table V. Wait-States
Memory Mapped Registers (New to the ADSP-2189M)
The ADSP-2189M has three memory mapped registers that
differ from other ADSP-21xx Family DSPs. The slight modifi-
cations to these registers (Wait-State Control, Programmable
Flag and Composite Select Control and System Control) pro-
vide the ADSP-2189M’s wait-state and
BMS
control features.
WAIT-STATE CONTROL
15 14 13 12 11 10
1
1
1
1
1
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
DM(0x3FFE)
Address Range
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
Wait-State Register
IOWAIT0 and Wait-State Mode Select Bit
IOWAIT1 and Wait-State Mode Select Bit
IOWAIT2 and Wait-State Mode Select Bit
IOWAIT3 and Wait-State Mode Select Bit
Composite Memory Select (CMS)
DWAIT
IOWAIT3
IOWAIT2
IOWAIT1
IOWAIT0
WAIT STATE MODE SELECT (ADSP-2189M)
0 = NORMAL MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 7)
1 = 2N+1 MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 15)
Figure 6. Wait-State Control Register (ADSP-2189M)
PROGRAMMABLE FLAG & COMPOSITE SELECT CONTROL
15 14 13 12 11 10
1
1
1
1
1
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1
DM(0x3FE6)
The ADSP-2189M has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The
CMS
signal is generated
to have the same timing as each of the individual memory
select signals (PMS,
DMS, BMS, IOMS)
but can combine
their functionality.
When set, each bit in the CMSSEL register causes the
CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the
PMS
and
DMS
bits in the
CMSSEL register and use the
CMS
pin to drive the chip select
of the memory, and use either
DMS
or
PMS
as the additional
address bit.
The
CMS
pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the
CMS
signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the
BMS
bit.
Byte Memory Select (BMS)
BMWAIT
(BIT-15, ADSP-2189M)
CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11-IOM, 10BM, 9-DM, 8-PM)
Figure 7. Programmable Flag and Composite Select Con-
trol Register
SYSTEM CONTROL
15 14 13 12 11 10
0
0
0
0
0
1
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
1
1
0
1
DM(0x3FFF)
RESERVED, ALWAYS = 0
(ADSP-2189M)
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0 = FI, FO,
IRQ0, IRQ1,
SCLK
1 = SPORT1
PWAIT
PROGRAM MEMORY
WAIT STATES
DISABLE
BMS
(ADSP-2189M)
0 = ENABLE
BMS
1 = DISABLE
BMS,
EXCEPT WHEN MEMORY
STROBES ARE THREE-STATED
The ADSP-2189M’s
BMS
disable feature combined with the
CMS
pin lets you use multiple memories in the byte memory
space. For example, an EPROM could be attached to the
BMS
select, and an SRAM could be connected to
CMS.
Because
BMS
is enabled at reset, the EPROM would be used for boot-
ing. After booting, software could disable
BMS
and set the
CMS
signal to respond to
BMS,
enabling the SRAM.
Figure 8. System Control Register
REV. A
–9–
AD [ ANALOG DEVICES ]
