Timing Diagrams — SRAM
Read Cycle Timing Diagrams
Read Cycle 1 (SCE = OE = V
IL
, SWE = V
IH
)
t
RC
A
0-18
t
AA
t
OH
D
I/O
Previous Data Valid
Data Valid
SCE
t
AS
SWE
S
EE
N
OTE
Write Cycle Timing Diagrams
Write Cycle (SWE Controlled, OE = V
IH
)
t
WC
A
0-18
t
AW
t
CW
t
AH
t
WP
t
WHZ
t
DW
Data Valid
t
DW
t
DH
D
I/O
Read Cycle 2 (SWE = V
IH
)
t
RC
A
0-18
t
AA
SCE
t
ACE
t
CLZ
S
EE
N
OTE
Write Cycle (SCE Controlled, OE = V
IH
)
t
WC
A
0-18
t
AW
t
CHZ
S
EE
N
OTE
t
AH
t
CW
t
AS
SCE
OE
t
WP
t
OE
t
OLZ
S
EE
N
OTE
t
OHZ
S
EE
N
OTE
SWE
t
DW
D
I/O
Data Valid
t
DH
D
I/O
High Z
Data Valid
UNDEFINED
DON’T CARE
Note: Guaranteed by design, but not tested.
AC Test Circuit
Current Source
I
OL
AC Test Conditions
Parameter
Typical
0 – 3.0
5
1.5
Units
V
ns
V
To Device Under Test
C
L
= 50 pF
V
Z
~ 1.5 V (Bipolar Supply)
Input Pulse Level
Input Rise and Fall
Input and Output Timing Reference Level
I
OH
Current Source
Notes:
1) V
Z
is programmable from -2V to +7V. 2) I
OL
and I
OH
programmable from 0 to 16 mA. 3) Tester Impedance
Z
O
= 75Ω.
4)
V
Z
is typically the midpoint of V
OH
and V
OL
. 5) I
OL
and I
OH
are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
Aeroflex Circuit Technology
4
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
