Timing Diagrams — SRAM
Read Cycle Timing Diagrams
Write Cycle Timing Diagrams
Write Cycle (SWE Controlled, OE = VIH)
Read Cycle 1 (SCE = OE = VIL, SWE = VIH)
tWC
tRC
A0-18
A0-18
tAA
tAW
tCW
tAH
tOH
DI/O
SCE
Previous Data Valid
Data Valid
tAS
tWP
SWE
tDW
tDH
tWHZ
tDW
SEE NOTE
DI/O
Data Valid
Read Cycle 2 (SWE = VIH)
tRC
Write Cycle (SCE Controlled, OE = VIH )
A0-18
tWC
tAA
A0-18
tAH
tAW
SCE
tAS
tACE
tCW
tWP
tCHZ
SEE NOTE
SCE
tCLZ
SEE NOTE
OE
tOHZ
tOE
SWE
SEE NOTE
tOLZ
SEE NOTE
tDW
tDH
DI/O
Data Valid
High Z
DI/O
Data Valid
Note: Guaranteed by design, but not tested.
DON’T CARE
UNDEFINED
AC Test Circuit
Current Source
IOL
AC Test Conditions
Parameter
Typical
0 – 3.0
5
Units
Input Pulse Level
Input Rise and Fall
V
ns
V
VZ ~ 1.5 V (Bipolar Supply)
To Device Under Test
CL = 50 pF
Input and Output Timing Reference Level
1.5
IOH
Current Source
Notes:
1) VZ is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance
ZO = 75Ω. 4) VZ is typically the midpoint of VOH and VOL. 5) IOL and IOH are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
4
Aeroflex Circuit Technology
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
