Pin Description
Signal
RX DATA 0/1
Direction
INPUT
Signal Description
Positive Data In.
This should be a TTL description of the positive, half of the
Manchester code data on the bus. It should be driven to a logic level “1” when
a predetermined positive threshold is exceeded on the bus.
Negative Data In.
This should be a TTL description of the negative half of the
Manchester code data on the bus. It should be driven to a logic level “1” when
a predetermined negative threshold is exceeded on the bus.
Transmitter Inhibit Bus 0.
Normally high. Goes low when the transmitter is
transmitting. Should be used to Inhibit the bus "0" driver.
Transmitter Inhibit Bus 1.
Normally high. Goes low when the transmitter is
transmitting. Should be used to Inhibit the bus "1" driver.
Positive Data Out
- When this signal goes high the bus should be driven
positive.
Negative Data Out
- When this signal goes high the bus should be driven
negative.
RT address lines
- These should be hardwired by the user. RTAD4 is the most
significant bit.
RT address parity line
- This must be hardwired by the user to give odd parity.
Built-ln Test Decode
- When held low, prevents resetting TXTO Bit, HSFAIL
Bit, and LTFAIL Bit in the BIT Word (as well as TF and SSF Bits in the Status
Word) upon receipt of a Transmit Bit Word Mode Command.
Broadcast command enable Bus 0/1
- When low the recognition of
broadcast command is prevented on both Bus 0 and 1.
CT1991 only.
Broadcast command enable Bus 0
- When low the recognition of broadcast
command is prevented on Bus 0.
CT1990 only.
Broadcast command enable Bus 1
- When low the recognition of broadcast
command is prevented on Bus 1.
CT1990 only.
6 Megahertz master clock.
Internal Highway
- Bi-directional 8 bit highway on which 16 bit words are
passed in two bytes. IH 715 is the most significant bit of each byte, the most
significant byte being transferred first. The highway should only be driven by
the subsystem when data is to be transferred to the RT.
RX DATA 0/1
INPUT
TX INHIBIT 0
TX INHIBIT 1
TX DATA
TX DATA
RTAD 0-4
RTADPAR
BIT DECODE
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
BCSTEN 0/1
BCSTEN 0
BCSTEN 1
6MCK
IH 08 (LSB)
IH 19
IH 210
IH 311
IH 412
IH 513
IH614
IH715 (MSB)
DTRQ
DTAK
IUSTB
H/L
GBR
INPUT
INPUT
INPUT
INPUT
BI-DIRECTIONAL
OUTPUT
INPUT
OUTPUT
OUTPUT
OUTPUT
Data Transfer Request
- Goes low to request a data transfer between the
ASIC and subsystem. Goes high at the end of the transfer.
Data Transfer Acknowledge
- Goes low to indicate that the subsystem is
ready for the data transfer.
Interface Unit Strobe
- This is a double pulse strobe used to transfer the two
bytes of data
High/Low
- Indicates which byte of data is on the internal highway. Logic level
"0" for least significant byte.
Good Block Received
- Pulses low for 500ns when a block of data has been
received by the ASIC and has passed all the validity and error checks.
10
Aeroflex Circuit Technology
SCDCT1990 REV B 8/21/00 Plainview NY (516) 694-6700
AEROFLEX [ AEROFLEX CIRCUIT TECHNOLOGY ]
