Data Sheet
January 1999
Quad Differential Drivers
BDG1A, BDP1A, BDGLA, BPNGA, BPNPA, and BPPGA
The HBM ESD threshold voltage presented here was
obtained by using these circuit parameters.
Table 5. Typical ESD Thresholds for Data
Transmission Drivers
Device
BDG1A, BDGLA
BDP1A
BPPGA, BPNGA,
BPNPA
HBM
Threshold
>2500
>2500
>3000
CDM
Threshold
>1000
>2000
>2000
ESD Failure Models
Lucent employs two models for ESD events that can
cause device damage or failure.
1. A human-body model (HBM) that is used by most
of the industry for ESD-susceptibility testing and
protection-design evaluation. ESD voltage thresh-
olds are dependent on the critical parameters used
to define the model. A standard HBM (resistance =
1500
Ω,
capacitance = 100 pF) is widely used and,
therefore, can be used for comparison purposes.
2. A charged-device model (CDM), which many
believe is the better simulator of electronics manu-
facturing exposure.
Tables 5 and 6 illustrate the role these two models play
in the overall prevention of ESD damage. HBM ESD
testing is intended to simulate an ESD event from a
charged person. The CDM ESD testing simulates
charging and discharging events that occur in produc-
tion equipment and processes, e.g., an integrated cir-
cuit sliding down a shipping tube.
Table 6. ESD Damage Protection
ESD Threat Controls
Personnel
Control
Wrist straps
ESD shoes
Antistatic flooring
Human-body model
(HBM)
Processes
Static-dissipative
materials
Air ionization
Charged-device
model (CDM)
Model
Latch-Up
Latch-up evaluation has been performed on the data transmission drivers. Latch-up testing determines if power-
supply current exceeds the specified maximum due to the application of a stress to the device under test. A device
is considered susceptible to latch-up if the power supply current exceeds the maximum level and remains at that
level after the stress is removed.
Lucent performs latch-up testing per an internal test method that is consistent with JEDEC Standard No. 17 (previ-
ously JC-40.2) “CMOS Latch-Up Standardized Test Procedure.”
Latch-up evaluation involves three separate stresses to evaluate latch-up susceptibility levels:
1. dc current stressing of input and output pins.
2. Power supply slew rate.
3. Power supply overvoltage.
Table 7. Latch-Up Test Criteria and Test Results
dc Current Stress of
I/O Pins
≥150
mA
≥250
mA
Power Supply
Slew Rate
≤1
µs
≤100
ns
Power Supply
Overvoltage
≥1.75 ×
Vmax
≥2.25 ×
Vmax
Data Transmission
Driver ICs
Minimum Criteria
Test Results
Based on the results in Table 6, the data transmission drivers pass the Lucent latch-up testing requirements and
are considered not susceptible to latch-up.
Lucent Technologies Inc.
9
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