Quad Differential Receivers
BRF1A, BRF2A, BRS2B, BRR1A, and BRT1A
Data Sheet
April 2001
Timing Characteristics
Table 4. Timing Characteristics
(See Figure 4 and Figure 5.)
For propagation delays (t
PLH
and t
PHL
) over the temperature range, see Figure 9 and Figure 10.
Propagation delay test circuit connected to output is shown in Figure 6.
T
A
= –40 °C to +125 °C, V
CC
= 5 V
±
0.5 V.
Parameter
Symbol
Min
1.5
1.5
—
—
—
—
—
—
—
—
—
—
—
Typ
2.5
2.5
5
5
—
—
0.8
—
—
8
8
—
—
Max
4.0
4.0
12
12
0.7
4.0
1.4
1.5
0.3
12
12
3.0
3.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Propagation Delay:
Input to Output High
t
PLH
Input to Output Low
t
PHL
Disable Time, C
L
= 5 pF:
High-to-high Impedance
t
PHZ
Low-to-high Impedance
t
PLZ
Pulse Width Distortion, ltpHL
−
tpLHI:
Load Capacitance (C
L
) = 15 pF
tskew1
Load Capacitance (C
L
) = 150 pF
tskew1
Output Waveform Skews:
Part-to-Part Skew, T
A
= 75 °C
∆tskew1p-p
Part-to-Part Skew, T
A
= –40 °C to +125 °C
∆tskew1p-p
Same Part Skew
∆tskew
Enable Time:
High Impedance to High
t
PZH
High Impedance to Low
t
PZL
Rise Time (20%—80%)
t
tLH
Fall Time (80%—20%)
t
tHL
EXTRINSIC PROPAGATION DELAY, t
P
(ns)
7
6
5
4
t
PLH
(TYP)
3
2
t
PHL
(TYP)
1
0
0
25
50
75
100
125
150
175 200
LOAD CAPACITANCE, C
L
(pF)
12-3462(F)
Note: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the sum of the
delay due to the external capacitance and the intrinsic delay of the device.
Figure 3. Typical Extrinsic Propagation Delay vs. Load Capacitance at 25 °C
4
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
