Data Sheet, Rev. 3
June 2001
FW802A Low-Power PHY
IEEE
1394A-2000
Two-Cable Transceiver/Arbiter Device
Two of the signals are used to set up various test
conditions used in manufacturing. These signals (SE
and SM) should be connected to V
SS
for normal
operation.
Description
(continued)
to become active in order to respond to the event or to
notify the LLC of the event (e.g., incoming bias or dis-
connection is detected on a suspended port, a new
connection is detected on a nondisabled port, etc.).
The SYSCLK output will become active (and the PHY/
link interface will be initialized and become operative)
within 3 ms after LPS is asserted high, when the
FW802A is in the low-power mode.
CPS
LPS
/ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PC0
PC1
PC2
C/LKON
SE
SM
LINK
INTERFACE
I/O
TPA0+
TPA0–
ARBITRATION
AND
CONTROL
STATE
MACHINE
LOGIC
RECEIVED
DATA
DECODER/
RETIMER
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
R0
R1
TPBIAS0
CABLE PORT 0
TPB0+
TPB0–
PD
TPA1+
TPA1–
TPBIAS1
TPB1+
TPB1–
/RESET
TRANSMIT
DATA
ENCODER
CABLE PORT 1
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND
CLOCK
GENERATOR
XI
XO
5-5459.f (F)
Figure 1. Block Diagram
Agere Systems Inc.
5
AGERE [ AGERE SYSTEMS ]
