FW802A Low-Power PHY
IEEE
1394A-2000
Two-Cable Transceiver/Arbiter Device
Data Sheet, Rev. 3
June 2001
Signal Information
(continued)
Table 1. Signal Descriptions
(continued)
Pin
16
Signal*
LPS
Type
I
Name/Description
Link Power Status.
LPS is connected to either the V
DD
supplying the
LLC or to a pulsed output that is active when the LLC is powered for the
purpose of monitoring the LLC power status. If LPS is inactive for more
than 1.2
µs
and less than 25
µs,
interface is reset. If LPS is inactive for
greater than 25
µs,
the PHY will disable the PHY/Link interface to save
power. FW802A continues its repeater function.
Link Request.
LREQ is an output from the LLC that requests the PHY to
perform some service. Bus-keeper circuitry is built into this terminal.
No Connect.
Power-Class Indicators.
On hardware reset, these inputs set the default
value of the power class indicated during self-ID. These bits can be
programmed by tying the signals to V
DD
(high) or to ground (low).
Powerdown.
When asserted high, PD turns off all internal circuitry except
the bias-detect circuits that drive the CNA signal. Internal FW802A logic is
kept in the reset state as long as PD is asserted. PD terminal is provided
for backward compatibility. It is recommended that the FW802A be
allowed to manage its own power consumption using suspend/resume in
conjunction with LPS. C/LKON features are defined in 1394a-2000.
Power for PLL Circuit.
PLLV
DD
supplies power to the PLL circuitry
portion of the device.
Ground for PLL Circuit.
PLLV
SS
is tied to a low-impedance ground
plane.
Current Setting Resistor.
An internal reference voltage is applied to a
resistor connected between R0 and R1 to set the operating current and
the cable driver output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 kΩ
±
1% should be used to meet the
IEEE
1394-1995 standard requirements for output voltage limits.
Reset (Active-Low).
When /RESET is asserted low (active), the FW802A
is reset. An internal pull-up resistor, which is connected to V
DD
, is
provided, so only an external delay capacitor is required. This input is a
standard logic buffer and can also be driven by an open-drain logic output
buffer.
Test Mode Control.
SE is used during the manufacturing test and should
be tied to V
SS
.
Test Mode Control.
SM is used during the manufacturing test and should
be tied to V
SS
.
System Clock.
SYSCLK provides a 49.152 MHz clock signal, which is
synchronized with the data transfers to the LLC.
1
44, 45, 46,
47, 48
20
21
22
19
LREQ
NC
PC0
PC1
PC2
PD
I
—
I
I
57
58
54
55
61
PLLV
DD
PLLV
SS
R0
R1
/RESET
—
—
I
I
28
29
63
36
41
SE
SM
SYSCLK
TPA0+
TPA1+
I
I
O
Analog I/O
Portn, Port Cable Pair A.
TPAn is the port A connection to the twisted-
pair cable. Board traces from each pair of positive and negative differen-
tial signal pins should be kept matched and as short as possible to the
external load resistors and to the cable connector.
* Active-low signals are indicated by “/” at the beginning of signal names, within this document.
8
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
