USS-820FD
USB Device Controller
Data Sheet, Rev. 1
August 2004
Register Interface (continued)
Table 26. Transmit FIFO Flag Register (TXFLG)—Address: 04H; Default: 0000 1000B (continued)
Bit
Symbol
Function/Description
0
TXOVF
Transmit FIFO Overrun Flag (Read, Clear Only). This bit is set when an additional byte
is written to a full FIFO, or TXCNT is written while TXFIF[1:0] = 11. This bit must be
cleared by firmware through TXCLR. When this bit is set, the FIFO is in an unknown state;
thus, it is recommended that the FIFO is reset in the error management routine using the
TXCLR bit in TXCON.
When the transmit FIFO overruns, the write pointer does not advance; it remains locked in
the full position. Check this bit after loading the FIFO prior to writing the byte count
register.
When this bit is set, all transmissions are NACKed.
In isochronous mode, TXOVF, TXURF, and TXFIF are handled using the following rule:
firmware events cause status change immediately, while USB events cause status change
only at SOF. Since overrun can only be caused by firmware, TXOVF is updated immedi-
ately. Check the TXOVF flag after writing to the transmit FIFO before writing to TXCNT.
Table 27. Receive FIFO Data Register (RXDAT)—Address: 05H; Default: 0000 0000B
Receive FIFO data specified by EPINDEX is stored and read from this register. This register is endpoint indexed.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXDAT[7:0]
R
Bit
7:0
Symbol
Function/Description
RXDAT[7:0] Receive FIFO Data Register (Read Only). To write to the receive FIFO, the SIE writes
to this register. To read data from the receive FIFO, the CPU reads from this register.
The write pointer and read pointer are incremented automatically after a write and read,
respectively.
The EPINDEX register must not be changed during a sequence of RXDAT reads of a
particular data set. See the Receive FIFO section for more details.
Agere Systems Inc.
29
AGERE [ AGERE SYSTEMS ]
