USS-820FD
USB Device Controller
Data Sheet, Rev. 1
August 2004
Register Interface (continued)
Table 28. Receive FIFO Byte-Count High and Low Registers (RXCNTH, RXCNTL)—Address: RXCNTH =
07H, RXCNTL = 06H; Default: RXCNTH = 0000 0000B, RXCNTL = 0000 0000B
High and low registers are in a two-register ring buffer that is used to store the byte count for the data packets
received in the receive FIFO specified by EPINDEX. These registers are endpoint indexed.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
—
—
BC9
BC8
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
R
Bit
Symbol
Function/Description
Reserved. Write 0s to these bits. Reads always return 0s.
15:10
9:0
—
BC[9:0]
Receive Byte Count (Read Only). 10-bit, ring buffer byte. Stores receive byte count
(RXCNT).
Table 29. Receive FIFO Control Register (RXCON)—Address: 08H; Default: 0000 0100B
Controls the receive FIFO specified by EPINDEX. This register is endpoint indexed.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RXCLR
FFSZ1
FFSZ0
RXFFRC
RXISO
ARM
ADVWM
REVWP
R/W
Bit
Symbol
Function/Description
7
RXCLR Receive FIFO Clear. Setting this bit flushes the receive FIFO, resets all the read/write
pointers and markers, resets the RXSETUP, STOVW, EDOVW, RXVOID, RXERR, and
RXACK bits of the RXSTAT register, sets the RXEMP bit in RXFLG register, and clears all
other bits in RXFLG register. Hardware clears this bit when the flush operation is
completed. Setting this bit does not affect the RXSEQ bit of RXSTAT. This bit should only
be set when the endpoint is disabled or there is a FIFO error present. Firmware should
never set this bit to clear a SETUP packet. The next SETUP packet will automatically clear
the receive FIFO.
6:5
FFSZ[1:0] FIFO Size. These bits select the size of the receive FIFO.
FFSZ[1:0] Nonisochronous Size Isochronous Size
00
01
10
11
16
64
8*
64
256
512
1024
32*
* Assumes MCSR.FEAT = 1. If MCSR.FEAT = 0, these FFSZ settings indicate 64 bytes.
30
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
