Data Sheet
June 1999
ORCA
Series 3C and 3T FPGAs
Timing Characteristics
(continued)
Table 44. Synchronous Memory Write Characteristics
OR3Cxx Commercial: V
DD
= 5.0 V ± 5%, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 5.0 V ± 10%, –40 °C
<
T
A
<
+85 °C.
OR3Txxx Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 3.0 V to 3.6 V, –40 °C
<
T
A
<
+85 °C.
Speed
Parameter
Write Operation for RAM Mode:
Maximum Frequency
Clock Low Time
Clock High Time
Clock to Data Valid (CLK to F[6, 4, 2, 0])*
Write Operation Setup Time:
Address to Clock (CIN to CLK)
Address to Clock (DIN[7, 5, 3, 1] to CLK)
Data to Clock (DIN[6, 4, 2, 0] to CLK)
Write Enable (WREN) to Clock (ASWE to CLK)
Write-port Enable 0 (WPE0) to Clock (CE to
CLK)
Write-port Enable 1 (WPE1) to Clock (LSR to
CLK)
Write Operation Hold Time:
Address from Clock (CIN from CLK)
Address from Clock (DIN[7, 5, 3, 1] from CLK)
Data from Clock (DIN[6, 4, 2, 0] from CLK)
Write Enable (WREN) from Clock (ASWE from
CLK)
Write-port Enable 0 (WPE0) from Clock (CE
from CLK)
Write-port Enable 1 (WPE1) from Clock (LSR
from CLK)
Symbol
Min
SMCLK_FRQ
SMCLKL_MPW
SMCLKH_MPW
MEM_DEL
WA4_SET
WA_SET
WD_SET
WE_SET
WPE0_SET
WPE1_SET
-4
Max
151.00
—
—
10.00
—
—
—
—
—
—
-5
Min
—
1.80
2.77
—
0.99
0.52
0.06
0.16
1.69
2.13
-6
Max
Min
—
1.32
2.13
—
0.71
0.35
0.00
0.14
1.16
1.58
-7
Max
Min
—
1.05
1.62
—
0.58
0.28
0.00
0.12
0.84
1.31
Unit
Max
—
2.34
3.79
—
1.25
0.72
0.02
0.18
2.25
2.79
197.00
—
—
7.14
—
—
—
—
—
—
254.00
—
—
5.00
—
—
—
—
—
—
315.00 MHz
ns
ns
4.08
ns
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
WA4_HLD
WA_HLD
WD_HLD
WE_HLD
WPE0_HLD
WPE1_HLD
0.00
0.00
0.59
0.03
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.42
0.00
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.40
0.08
0.00
0.00
—
—
—
—
—
—
0.00
0.00
0.32
0.06
0.00
0.00
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
* The RAM is written on the inactive clock edge following the active edge that latches the address, data, and control signals.
Note: The table shows worst-case delays.
ORCA
Foundry reports the delays for individual paths within a group of paths representing the same
timing parameter and may accurately report delays that are less than those listed.
WA4_SET
WA_SET
CIN, DIN[7, 5, 3, 1]
WD_SET
DIN[6, 4, 2, 0]
WE_SET
ASWE (WREN)
WPE0_SET
WPE1_SET
CE (WPE0),
LSR (WPE1)
T
SCH
CK
MEM_DEL
F[6, 4, 2, 0]
T
SCL
WPE0_HLD
WPE1_HLD
WE_HLD
WD_HLD
WA4_HLD
WA_HLD
5-4621(F)
Figure 65. Synchronous Memory Write Characteristics
Lucent Technologies Inc.
109
AGERE [ AGERE SYSTEMS ]
