OR3T30-5BA256 参数 Datasheet PDF下载

ORCA

Series 3C and 3T FPGAs

Data Sheet

June 1999

Timing Characteristics

(continued)

Table 57. OR3C/Txxx Input to ExpressCLK (ECLK) Fast-Capture Setup/Hold Time (Pin-to-Pin)

OR3Cxx Commercial: V

DD

= 5.0 V ± 5%, 0 °C

<

T

A

<

70 °C; Industrial: V

DD

= 5.0 V ± 10%, –40 °C

<

T

A

<

+85 °C.

OR3Txxx Commercial: V

DD

= 3.0 V to 3.6 V, 0 °C

<

T

A

<

70 °C; Industrial: V

DD

= 3.0 V to 3.6 V, –40 °C

<

T

A

<

+85 °C.

Description

(T

J

= 85 °C, V

DD

= min)

Input to ECLK Setup Time (middle

ECLK pin)

Speed

Device

Min

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

OR3T20

OR3T30

OR3C/T55

OR3C/T80

OR3T125

—

—

1.36

1.25

—

—

—

6.91

6.79

—

—

—

0.00

0.00

—

—

—

4.94

4.82

—

—

—

0.00

0.00

—

—

—

0.00

0.00

—

-4

Max

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Min

1.34

1.30

1.22

1.14

1.03

6.30

6.27

6.19

6.11

6.00

0.00

0.00

0.00

0.00

0.00

4.39

4.35

4.28

4.21

4.10

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

-5

Max

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Min

0.88

0.86

0.83

0.80

0.76

5.32

5.30

5.27

5.24

5.20

0.00

0.00

0.00

0.00

0.00

3.51

3.40

3.18

2.98

2.63

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

-6

Max

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Min

0.83

0.82

0.80

0.77

0.74

5.98

5.97

5.95

5.93

5.90

0.00

0.00

0.00

0.00

0.00

4.41

4.31

4.11

3.91

3.61

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

0.00

-7

Max

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Input to ECLK Setup Time (middle

ECLK pin, delayed data input)

Input to ECLK Setup Time (corner

ECLK pin)

Input to ECLK Setup Time (corner

ECLK pin, delayed data input)

Input to ECLK Hold Time (middle

ECLK pin)

Input to ECLK Hold Time (middle

ECLK pin, delayed data input)

Note:

The pin-to-pin timing parameters in this table should be used instead of results reported by

ORCA

Foundry.

The ECLK delays are to all of the PIOs on one side of the device for middle pin input, or two sides of the device for corner pin input. The delay

includes both the input buffer delay and the clock routing to the PIO clock input.

128

Lucent Technologies Inc.