OR3T30-5BA256 参数 Datasheet PDF下载

ORCA

Series 3C and 3T FPGAs

Data Sheet

June 1999

Timing Characteristics

(continued)

Table 58. OR3C/Txxx Input to Fast Clock Setup/Hold Time (Pin-to-Pin)

OR3Cxx Commercial: V

DD

= 5.0 V ± 5%, 0 °C

<

T

A

<

70 °C; Industrial: V

DD

= 5.0 V ± 10%, –40 °C

<

T

A

<

+85 °C.

OR3Txxx Commercial: V

DD

= 3.0 V to 3.6 V, 0 °C

<

T

A

<

70 °C; Industrial: V

DD

= 3.0 V to 3.6 V, –40 °C

<

T

A

<

+85 °C.

Description

(T

J

= 85 °C, V

DD

= min)

Speed

Device

Min

-4

Max

Min

-5

Max

Min

-6

Max

Min

-7

Max

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Unit

Output Not on Same Side of Device As Input Clock (Fast Clock Delays Using ExpressCLK Inputs)

Input to FCLK Setup Time (middle

OR3T20

—

—

0.00

—

0.00

—

0.00

ECLK pin)

OR3T30

—

—

0.00

—

0.00

—

0.00

OR3C/T55

0.00

—

0.00

—

0.00

—

0.00

OR3C/T80

0.00

—

0.00

—

0.00

—

0.00

OR3T125

—

—

0.00

—

0.00

—

0.00

Input to FCLK Setup Time (middle

OR3T20

—

—

0.80

—

0.58

—

2.20

ECLK pin, delayed data input)

OR3T30

—

—

0.74

—

0.55

—

2.17

OR3C/T55

0.29

—

0.62

—

0.51

—

2.11

OR3C/T80

0.14

—

0.50

—

0.46

—

2.06

OR3T125

—

—

0.22

—

0.33

—

1.90

Input to FCLK Setup Time (corner

OR3T20

—

—

0.00

—

0.00

—

0.00

ECLK pin)

OR3T30

—

—

0.00

—

0.00

—

0.00

OR3C/T55

0.00

—

0.00

—

0.00

—

0.00

OR3C/T80

0.00

—

0.00

—

0.00

—

0.00

OR3T125

—

—

0.00

—

0.00

—

0.00

Input to FCLK Setup Time (corner

OR3T20

—

—

0.00

—

0.00

—

0.00

ECLK pin, delayed data input)

OR3T30

—

—

0.00

—

0.00

—

0.00

OR3C/T55

0.00

—

0.00

—

0.00

—

0.00

OR3C/T80

0.00

—

0.00

—

0.00

—

0.00

OR3T125

—

—

0.00

—

0.00

—

0.00

Input to FCLK Hold Time (middle

OR3T20

—

—

4.29

—

3.72

—

3.27

ECLK pin)

OR3T30

—

—

4.50

—

3.80

—

3.35

OR3C/T55

6.33

—

4.97

—

3.96

—

3.52

OR3C/T80

6.95

—

5.49

—

4.15

—

3.72

OR3T125

—

—

6.36

—

4.47

—

4.05

Notes:

The pin-to-pin timing parameters in this table should be used instead of results reported by

ORCA

Foundry.

The FCLK delays are for a fully routed clock tree that uses the ExpressCLK input into the fast clock network. It includes both the input buffer

delay and the clock routing to the PFU CLK input. The delay will be reduced if any of the clock branches are not used.

130

Lucent Technologies Inc.