ORCA
Series 3C and 3T FPGAs
Data Sheet
June 1999
Timing Characteristics
(continued)
PIO Timing
Table 48. Programmable I/O (PIO) Timing Characteristics
OR3Cxx Commercial: V
DD
= 5.0 V ± 5%, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 5.0 V ± 10%, –40 °C
<
T
A
<
+85 °C.
OR3Txxx Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 3.0 V to 3.6 V, –40 °C
<
T
A
<
+85 °C.
Speed
Parameter
Input Delays
(T
J
= 85 °C, V
DD
= min)
Input Rise Time
Input Fall Time
PIO Direct Delays:
Pad to In (pad to CLK IN)
Pad to In (pad to IN1, IN2)
Pad to In Delayed (pad to IN1, IN2)
PIO Transparent Latch Delays:
Pad to In (pad to IN1, IN2)
Pad to In Delayed (pad to IN1, IN2)
IN_RIS
IN_FAL
CKIN_DEL
IN_DEL
IND_DEL
LATCH_DEL
LATCHD_DEL
—
—
—
—
—
—
—
500
500
1.41
2.16
9.05
4.11
10.58
—
—
—
—
—
—
—
—
—
—
—
—
4.05
4.08
6.11
5.89
5.38
—
—
—
—
—
—
—
4.82
11.03
1.42
7.36
1.64
1.45
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
500
500
1.26
1.87
7.83
3.25
9.05
—
—
—
—
—
—
—
—
—
—
—
—
3.14
3.19
4.76
4.66
4.22
—
—
—
—
—
—
—
3.63
9.18
0.71
5.91
1.29
1.14
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
500
500
0.64
1.28
6.64
2.52
7.67
—
—
—
—
—
—
—
—
—
—
—
—
2.53
2.62
3.81
3.57
3.44
—
—
—
—
—
—
—
3.23
9.68
0.50
7.06
1.00
0.89
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
500
500
0.41
0.90
7.27
1.82
7.65
—
—
—
—
—
—
—
—
—
—
—
—
2.05
2.14
3.17
2.98
2.88
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
Min
-4
Max
Min
-5
Max
Min
-6
Max
Min
-7
Max
Unit
Input Latch/FF Setup Timing:
INREGE_SET 5.93
Pad to ExpressCLK (fast-capture latch/FF)
INREGED_SET 12.86
Pad Delayed to ExpressCLK
(fast-capture latch/FF)
INREG_SET
1.62
Pad to Clock (input latch/FF)
INREGD_SET 8.57
Pad Delayed to Clock (input latch/FF)
INCE_SET
2.03
Clock Enable to Clock (CE to CLK)
INLSR_SET
1.79
Local Set/Reset (sync) to Clock (LSR to CLK)
Input FF/Latch Hold Timing:
Pad from ExpressCLK (fast-capture latch/FF)
Pad Delayed from ExpressCLK
(fast-capture latch/FF)
Pad from Clock (input latch/FF)
Pad Delayed from Clock (input latch/FF)
Clock Enable from Clock (CE from CLK)
Local Set/Reset (sync) from Clock
(LSR from CLK)
Clock-to-in Delay (FF CLK to IN1, IN2)
Clock-to-in Delay (latch CLK to IN1, IN2)
Local S/R (async) to IN (LSR to IN1, IN2)
Local S/R (async) to IN (LSR to IN1, IN2)
LatchFF in Latch Mode
Global S/R to In (GSRN to IN1, IN2)
INREGE_HLD
INREGED_HLD
INREG_HLD
INREGD_HLD
INCE_HLD
INLSR_HLD
INREG_DEL
INLTCH_DEL
INLSR_DEL
INLSRL_DEL
INGSR_DEL
0.00
0.00
0.00
0.00
0.00
0.00
—
—
—
—
—
Note: The delays for all input buffers assume an input rise/fall time of
<1
V/ns.
112
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
