Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
Table 49. Microprocessor Interface (MPI) Timing Characteristics (continued)
DD = 5.0 V ± 5%, 0 °C < TA < 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C < TA < +85 °C.
OR3Cxx Commercial: V
OR3Txxx Commercial: V
<
<
<
<
A
T +85 °C.
DD
A
T
DD
= 3.0 V to 3.6 V, 0 °C
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
Speed
Parameter
Symbol
–4
–5
–6
–7
Unit
Min Max Min Max Min Max Min Max
User Logic Delay(5)
User Logic Delay
USTART_DEL
—
—
—
—
—
3.6
7.5
—
—
—
—
—
—
3.4
7.3
—
—
—
—
—
—
3.3
7.1
—
—
—
—
—
—
2.8
6.0
—
ns
ns
ns
ns
User Start Delay (MPI_CLK falling to USTART)(6)
User Start Clear Delay (MPI_CLK to USTART)
User End Delay (USTART low to UEND low)(7)
Synchronous User Timing:
USTARTCLR_DEL
UEND_DEL
User End Setup (UEND to MPI_CLK)
User End Hold (UEND to MPI_CLK)
Data Setup for Read (D[7:0] to MPI_CLK)(9)
Data Hold for Read (D[7:0] from MPI_CLK)(9)
Asynchronous User Timing:
UEND_SET
UEND_HLD
RDS_SET
RDS_HLD
0.00
1.0
—
—
—
—
—
0.00
0.95
—
—
—
—
—
0.00
0.88
—
—
—
—
—
0.00
0.75
—
—
—
—
—
ns
ns
ns
ns
—
—
—
—
User End to Read Data Delay (UEND to
D[7:0])(10)
RDA_DEL
—
—
—
—
—
—
—
—
ns
Data Hold from User Start (low)(9)
Interrupt Request Pulse Width(8)
RDA_HLD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
TUIRQ_PW
1. For user system flexibility, CS0 and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when
MPI_STRB is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and CS0 and CS1 may go
inactive before the end of the read/write cycle.
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
5. User Logic Delay has no predefined value. The user must generate a UEND signal to complete the cycle.
6. USTART_DEL is based on the falling clock edge.
7. There is no specific time associated with this delay. The user must assert UEND low to complete this cycle.
8. The user must assert interrupt request low until a service routine is executed.
9. This should be at least one MPI_CLK cycle.
10. User should set up read data so that RDS_SET and RDS_HLD can be met for the microprocessor timing.
Notes:
PowerPC i960
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host (
,
) from the FPGA.
i960
timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
PowerPC
and
116
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
