Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Pin Information (continued)
Table 67. Pin Descriptions
(continued)
Symbol
I/O
Description
Special-Purpose Pins (continued)
A11/MPI_IRQ
A10/MPI_BI
A9/MPI_ACK
O
I/O
O
MPI active-low interrupt request output.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
PowerPC
mode MPI burst inhibit output.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
I/O
O
PowerPC
In
i960
mode MPI operation, this is the active-high transfer acknowledge (TA) output. For
MPI operation, it is the active-low ready/record (RDYRCV) output.
I/O After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
PowerPC
A8/MPI_RW
A7/MPI_CLK
A[4:0]
I
In
mode MPI operation, this is the active-low write/active-high read control signals.
i960
For
operation, it is the active-high write/active-low read control signal.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
I/O
I
PowerPC
This is the clock used for the synchronous MPI interface. For
, it is the CLKOUT
i960 i960
signal. For
, it is the system clock that is chosen for the
external bus interface.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
I/O
I
PowerPC
PowerPC
address inputs. The address bit mapping (in
For
operation, these are the
PowerPC
/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/A[4]. Note
i960
that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in
MPI mode.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
I/O
I
i960
i960
byte enable signals, BE[1:0], that are used as
A[1:0]/
For
operation, MPI_BE[1:0] provide the
i960
MPI_BE[1:0]
address bits A[1:0] in
byte-wide operation.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
I/O
I
D[7:0]
During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive
configuration data, and each pin has a pull-up enabled. During serial configuration modes, D0
PowerPC
microprocessor mode.
is the DIN input. D[7:0] are also the data pins for
i960
microprocessor mode and the
address/data pins for
After configuration, the pins are user-programmable I/O pins (see Note).
I/O
I
DIN
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. Dur-
ing configuration, a pull-up is enabled.
After configuration, this pin is a user-programmable I/O pin (see Note).
I/O
O
DOUT
During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
I/O
After configuration, DOUT is a user-programmable I/O pin (see Note).
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
152
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