Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Configuration readback can also be performed via the
MPI when it is in user mode. The MPI is enabled in user
mode by setting the MP_USER bit to 1 in the configura-
tion control register prior to the start of configuration or
through a configuration option. To perform readback,
the host processor writes the 14-bit readback start
address to the readback address registers and sets the
RD_CFG bit to 0 in the configuration control register.
Readback data is returned 8 bits at a time to the read-
back data register and is valid when the DATA_RDY bit
of the status register is 1. There is no error checking
during readback. A flow chart of the MPI readback
operation is shown in Figure 60. The RD_DATA pin
used for dedicated FPGA readback is invalid during
MPI readback.
FPGA Configuration Modes (continued)
There are two options for using the host interrupt
request in configuration mode. The configuration con-
trol register offers control bits to enable the interrupt on
either a bit stream error or to notify the host processor
when the FPGA is ready for more configuration data.
The MPI status register may be used in conjunction
with, or in place of, the interrupt request options. The
status register contains a 2-bit field to indicate the bit
stream error status. As previously mentioned, there is
also a bit to indicate the MPI’s readiness to receive
another byte of configuration data. A flow chart of the
MPI configuration process is shown in Figure 59. The
MPI status and configuration register bit maps can be
found in the Special Function Blocks section and MPI
configuration timing information is available in the Tim-
ing Characteristics section of this data sheet.
POWER ON WITH
VALID M[3:0]
TO DAISY-
DOUT
CHAINED
CCLK
DEVICES
8
D[7:0]
A[27:31]
CLKOUT
RD/WR
TA
D[7:0]
A[4:0]
WRITE CONFIGURATION
CONTROL REGISTER BITS
MPI_CLK
MPI_RW
MPI_ACK
MPI_BI
MPI_IRQ
MPI_STRB
CS0
ORCA
SERIES 3
FPGA
POWERPC
READ STATUS REGISTER
BI
IRQx
TS
A26
A25
DONE
INIT
NO
INIT = 1?
CS1
HDC
LDC
YES
5-5761(F)
READ STATUS REGISTER
Note: FPGA shown as a memory-mapped peripheral using CS0 and
CS1. Other decoding schemes are possible using CS0 and/or
CS1.
YES
DONE
DONE = 1?
Figure 57. PowerPC/MPI Configuration Schematic
NO
BIT STREAM ERROR?
NO
i960 SYSTEM CLOCK
YES
ERROR
8
TO DAISY-
CHAINED
DEVICES
DOUT
CCLK
AD[7:0]
D[7:0]
CLKIN
W/R
MPI_CLK
MPI_RW
MPI_ACK
MPI_IRQ
RDYRCV
XINTx
ALE
NO
ORCA
SERIES 3
FPGA
DATA_RDY = 1?
YES
MPI_ALE
MPI_STRB
MPI_BE0
MPI_BE1
i960
ADS
BE0
BE1
V
DD
DONE
INIT
HDC
LDC
WRITE DATA TO
CONFIGURATION DATA REG
CS1
CS0
5-5762(F)
5-5763(F)
Note: FPGA shown as only system peripheral with fixed chip select
signals. For multiperipheral systems, address decoding and/
or latching can be used to implement chip selects.
Figure 59. Configuration Through MPI
Figure 58. i960/MPI Configuration Schematic
Lucent Technologies Inc.
95
AGERE [ AGERE SYSTEMS ]
