Data Sheet
June 1999
ORCA Series 3C and 3T FPGAs
Timing Characteristics (continued)
(continued)
Table 60. General Configuration Mode Timing Characteristics
<
<
<
<
T +85 °C.
DD
A
DD
A
OR3Cxx Commercial: V
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
T
70 °C; Industrial: V
= 5.0 V ± 10%, –40 °C
DD
<
<
<
<
A
T
DD
A
OR3Txxx Commercial: V
T
70 °C; Industrial: V
= 3.0 V to 3.6 V, –40 °C
+85 °C.
Parameter
Slave Parallel Mode
Symbol
Min
Max
Unit
PO
Power-on Reset Delay
T
3.90
13.10
ms
CCLK
T
CCLK Period:
OR3Cxx
OR3Txxx
40.00
15.00
—
—
ns
ns
Configuration Latency (normal mode):
CL
T
OR3T20
OR3T30
OR3C55
OR3T55
OR3C80
OR3T80
OR3T125
0.36
0.47
1.94
0.72
2.81
1.05
1.64
—
—
—
—
—
—
—
ms
ms
ms
ms
ms
ms
ms
PR
T
Partial Reconfiguration (explicit mode):
OR3T20
OR3T30
OR3C55
OR3T55
OR3C80
OR3T80
OR3T125
0.48
0.54
1.72
0.65
2.04
0.77
0.93
—
—
—
—
—
—
—
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
µs/frame
INIT Timing
INIT_CCLK
T
INIT High to CCLK Delay:
Slave Parallel
Slave Serial
Master Serial:
(M3 = 1)
1.00
1.00
—
—
µs
µs
1.00
0.50
3.40
2.00
µs
µs
(M3 = 0)
Master Parallel:
(M3 = 1)
(M3 = 0)
4.80
1.00
16.20
3.60
µs
µs
IL
T
Initialization Latency (PRGM high to INIT high):
ms
ms
ms
ms
ms
OR3T20
OR3T30
OR3C/T55
OR3C/T80
OR3T125
0.21
0.24
0.30
0.36
0.45
0.68
0.79
1.00
1.20
1.50
INIT_WR
INIT High to WR, Asynchronous Peripheral
T
2.00
—
µs
Note: TPO is triggered when VDD reaches between 3.0 V to 4.0 V for the OR3Cxx and between 2.7 V and 3.0 V for the OR3Txxx.
134
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
