ORCA
Series 3C and 3T FPGAs
Data Sheet
June 1999
Timing Characteristics
(continued)
Table 63. Asynchronous Peripheral Configuration Mode Timing Characteristics
OR3Cxx Commercial: V
DD
= 5.0 V ± 5%, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 5.0 V ± 10%, –40 °C
<
T
A
<
+85 °C.
OR3Txxx Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C
<
T
A
<
70 °C; Industrial: V
DD
= 3.0 V to 3.6 V, –40 °C
<
T
A
<
+85 °C.
Parameter
WR, CS0, and CS1 Pulse Width
D[7:0] Setup Time:
3Cxx
3Txxx
D[7:0] Hold Time
RDY Delay
RDY Low
Earliest WR After RDY Goes High*
RD to D7 Enable/Disable
CCLK to DOUT
Symbol
T
WR
T
S
20.00
10.50
T
H
T
RDY
T
B
T
WR2
T
DEN
T
D
0.00
—
1.00
0.00
—
—
—
—
—
40.00
8.00
—
40.00
5.00
ns
ns
ns
ns
CCLK Periods
ns
ns
ns
Min
50.00
Max
—
Unit
ns
* This parameter is valid whether the end of not RDY is determined from the RDY pin or from the D7 pin.
Notes:
Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input on D[7:0].
D[6:0] timing is the same as the write data portion of the D7 waveform because D[6:0] are not enabled by
RD.
CS0
CS1
T
WR
WR
T
S
D7
WRITE DATA
T
H
T
WR2
T
DEN
T
DEN
RD
RDY
T
RDY
T
B
CCLK
T
D
DOUT
PREVIOUS BYTE
D7
D0
D1
D2
D3
5-4533(F)
Figure 85. Asynchronous Peripheral Configuration Mode Timing Diagram
138
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
