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    OR3T80-6PS240 参数 Datasheet PDF下载

    OR3T80-6PS240图片预览
    型号： OR3T80-6PS240
    PDF下载： 下载PDF文件 查看货源
    内容描述： 3C和3T现场可编程门阵列 [3C and 3T Field-Programmable Gate Arrays]
    分类和应用： 现场可编程门阵列可编程逻辑栅
    文件页数/大小： 210 页 / 4391 K
    品牌： AGERE [ AGERE SYSTEMS ]
     浏览型号OR3T80-6PS240的Datasheet PDF文件第202页浏览型号OR3T80-6PS240的Datasheet PDF文件第203页浏览型号OR3T80-6PS240的Datasheet PDF文件第204页浏览型号OR3T80-6PS240的Datasheet PDF文件第205页浏览型号OR3T80-6PS240的Datasheet PDF文件第206页浏览型号OR3T80-6PS240的Datasheet PDF文件第208页浏览型号OR3T80-6PS240的Datasheet PDF文件第209页浏览型号OR3T80-6PS240的Datasheet PDF文件第210页  
    Data Sheet
    June 1999
    ORCA
    Series 3C and 3T FPGAs
    E
    A
    Electrical Characteristics, 97, 98
    Error Checking (see FPGA Configuration)
    ExpressCLK, 1, 6, 31, 34, 37, 39, 41, 43, 47—51,
    70—74, 77—81
    (see also Clock distribution Network and
    Programmable Clock Manager)
    Index
    Absolute Maximum Ratings, 96
    AND-OR-INVERT (AOI), 6
    AND-OR-INVERT (AOI),1
    (see also Supplemental Logic
    Interconnect Cell (SLIC), 1
    Architecture
    Overview, 6—9
    ASWE, 9, 11, 15—17, 23, 33, 48
    F
    Fast Clock, 46—51, 54
    (see Clock Distribution Network)
    5 V Tolerant I/O 35
    Flexible Input Structure (FINS) 1, 27, 32
    (see also Routing)
    FPGA Configuration, 87—94
    Configuration Frame Format, 87
    Configuration Modes, 89
    Asynchronous Peripheral Mode, 91
    Daisy-Chaining, 95
    Master Parallel Mode, 89
    Master Serial Mode, 90
    Microprocessor Interface (MPI) Mode, 91
    Slave Parallel Mode, 94
    Slave Serial Mode, 94
    Data Format, 86
    Data Frame, 86
    Using
    ORCA
    Foundry to Generate RAM Data, 86
    FPGA States of Operation
    Configuration, 83
    Initialization, 82
    Other Configuration Options, 85
    Partial Reconfiguration, 85
    Reconfiguration, 85
    Start-Up, 84
    B
    Bidirectional Buffers (BIDIs), 6, 19, 43, 83
    (see also Routingand SLIC)
    Bit Stream (see FPGA Configuration)
    Bit Stream Error Checking, 88
    (see also FPGA states of Operation)
    Boundary Scan, 55
    (see Special Function Blocks)
    C
    Clock Control (CLKCNTRL), 50
    (see also Clock Distribution Network and
    Special Function Blocks)
    Clock Distribution Network, 48–51
    CLKCNTRL, 50
    ExpressCLK, 48
    Inputs, 51
    Fast Clock, 48, 51
    Global Control Signals, 48
    In the PICs
    ExpressCLK, 50
    System Clock, 50
    In the PLC Array
    Fast Clock, 49
    System Clock, 49
    PFU Clock Sources, 48
    Selecting Clock Input Pins, 51
    System Clock, 48
    To the PLC Array
    Fast Clock, 50
    System Clock, 50
    Clock Enable (CE), 9, 11, 17, 23, 31, 48
    Clock Multiplication (see PCM)
    Comparator (see LUT Operating Modes)
    Configuration (see FPGA States of Operation
    or FPGA Configuration)
    Control Inputs (see PICs, Inputs)
    I
    IEEE
    Standard, 1149.1 55, 59
    Initialization (see FPGA States of Operation)
    Input/Output Buffers
    Measurement Conditions, 138
    Output Buffer Characteristics
    OR3Cxx, 139
    OR3Txxx, 141
    J
    JTAG (see Boundry Scan)
    D
    Demultiplexing (see PICs, Input Demultiplexing), 38
    Duty-Cycle Adjustment (see PCM)
    Lucent Technologies Inc.
    207

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