Data Sheet
February 2004
Ambassador T8110L H.100/H.110 Switch
Table of Contents
Contents
Page
1
2
Introduction .........................................................................................................................................................1
1.1 Features....................................................................................................................................................1
Pin Description..................................................................................................................................................10
2.1
2.2
2.3
Interface Signals.....................................................................................................................................10
T8110L Pinout Information .....................................................................................................................12
Special Buffer Requirements..................................................................................................................20
2.3.1 H1x0 Bus Signal Internal Pull-Up/Pull-Down ..............................................................................20
2.3.2 Local Bus Signal Internal Pull-Up ...............................................................................................20
3
4
Main Architectural Features ..............................................................................................................................21
3.1 T8110L Architecture ...............................................................................................................................21
Microprocessor Interface ..................................................................................................................................22
4.1
4.2
4.3
Intel/Motorola Protocol Selector..............................................................................................................22
Word/Byte Addressing Selector..............................................................................................................22
Access Via the Microprocessor Bus .......................................................................................................23
4.3.1 Microprocessor Interface Register Map ......................................................................................24
4.3.2 Register Space Access...............................................................................................................28
4.3.3 Connection Memory Space Access............................................................................................28
4.3.4 Data Memory Space Access.......................................................................................................29
5
Operating Control and Status ...........................................................................................................................30
5.1
Control Registers....................................................................................................................................30
5.1.1 Reset Registers ..........................................................................................................................30
5.1.2 Master Output Enable Register...................................................................................................31
5.1.3 Connection Control—Data Memory Selector Register ...............................................................32
5.1.4 General Clock Control (Phase Alignment, Fallback, Watchdogs) Register ................................33
5.1.5 Phase Alignment Select Register ...............................................................................................33
5.1.6 Fallback Control Register............................................................................................................33
5.1.7 Fallback Type Select Register ....................................................................................................34
5.1.8 Fallback Trigger Registers..........................................................................................................35
5.1.9 Watchdog Select, C8, and NETREF Registers...........................................................................36
5.1.10 Watchdog EN Register ...............................................................................................................37
5.1.11 Failsafe Control Registers...........................................................................................................38
Error and Status Registers .....................................................................................................................39
5.2.1 Clock Errors ................................................................................................................................40
5.2.1.1 Transient Clock Errors Registers.................................................................................40
5.2.1.2 Latched Clock Error Register ......................................................................................41
5.2.2 System Status.............................................................................................................................42
5.2.2.1 Clock Fallback Status Register....................................................................................42
5.2.2.2 Device Identification Registers ....................................................................................43
5.2.2.3 System Device Errors..................................................................................................43
5.2
6
Clock Architecture.............................................................................................................................................44
6.1
Clock Input Control Registers.................................................................................................................45
6.1.1 Main Input Selector Register.......................................................................................................45
6.1.2 Main Divider Register..................................................................................................................46
6.1.3 Analog PLL1 (APLL1) Input Selector Register............................................................................46
6.1.4 APLL1 Rate Register ..................................................................................................................47
6.1.5 Main Inversion Select Register ...................................................................................................47
6.1.6 Resource Divider Register..........................................................................................................48
6.1.7 Analog PLL2 (APLL2) Rate Register ..........................................................................................48
6.1.8 LREF Input Select Registers.......................................................................................................49
6.1.9 DPLL1 Input Selector..................................................................................................................50
2
Agere Systems Inc.
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