Data Sheet
February 2004
Ambassador T8110L H.100/H.110 Switch
Table of Contents (continued)
Contents
Page
8.1.1 GPIO Data Register....................................................................................................................80
8.1.2 GPIO Read Mask Register .........................................................................................................81
8.1.3 GPIO R/W Register.....................................................................................................................81
8.1.4 GPIO Override Register..............................................................................................................82
GP Circuit Operation...............................................................................................................................82
8.2.1 GPIO General-Purpose Bits........................................................................................................83
8.2.2 GP Dual-Purpose Bits GPIO (Override)......................................................................................83
8.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only)..................................................83
8.2.3 GP External Interrupts ................................................................................................................83
8.2.4 GP Diagnostic Test Point Observation .......................................................................................83
8.2
9
Stream Rate Control .........................................................................................................................................84
9.1
H-Bus Stream Rate Control Registers....................................................................................................85
9.1.1 H-Bus Rate Registers .................................................................................................................85
L-Bus Stream Rate Control Registers ....................................................................................................85
9.2.1 L-Bus Rate Registers..................................................................................................................85
9.2.2 L-Bus 16.384 Mbits/s Operation .................................................................................................86
9.2.3 16.384 Mbits/s Local I/O Superrate ............................................................................................88
9.2.4 16.384 Mbits/s Local I/O Superrate ............................................................................................89
9.2
10 Error Reporting and Interrupt Control ...............................................................................................................90
10.1 Interrupt Control Registers......................................................................................................................90
10.1.1 Interrupts Via External FG[7:0] Registers ...................................................................................90
10.1.1.1 FGIO Interrupt Pending Register.................................................................................90
10.1.2 Interrupts Via External GP[7:0] ...................................................................................................92
10.1.2.1 GPIO Interrupt Pending Register.................................................................................92
10.1.2.2 GPIO Edge/Level and GPIO Polarity Registers ..........................................................93
10.1.3 Interrupts Via Internal System Errors..........................................................................................93
10.1.4 System Interrupt Pending High/Low Registers ...........................................................................94
10.1.5 System Interrupt Enable High/Low Registers .............................................................................95
10.1.6 Interrupts Via Internal Clock Errors.............................................................................................96
10.1.7 Clock Interrupt Pending High/Low Registers ..............................................................................97
10.1.8 Clock Interrupt Enable High/Low Registers ................................................................................98
10.1.9 Interrupt Servicing Registers.......................................................................................................99
10.1.9.1 Arbitration Control Register .........................................................................................99
10.1.9.2 SYSERR and CLKERR Output Select Register..........................................................99
10.1.9.3 Interrupt In-Service Registers....................................................................................101
10.2 Error Reporting and Interrupt Controller Circuit Operation ...................................................................103
10.2.1 Externally Sourced Interrupts Via FG[7:0], GP[7:0] ..................................................................104
10.2.2 Internally Sourced System Error Interrupts...............................................................................104
10.2.3 Internally Sourced Clock Error Interrupts..................................................................................104
10.2.4 Arbitration of Pending Interrupts ...............................................................................................104
10.2.4.1 Arbitration Off ............................................................................................................104
10.2.4.2 Flat Arbitration ...........................................................................................................104
10.2.4.3 Tier Arbitration...........................................................................................................104
10.2.4.4 Pre-Empting Disabled................................................................................................105
10.2.4.5 Pre-Empting Enabled ................................................................................................105
10.2.5 CLKERR Output........................................................................................................................105
10.2.6 SYSERR Output .......................................................................................................................105
10.2.7 System Handling of Interrupts...................................................................................................105
11 Test and Diagnostics ......................................................................................................................................106
11.1 Diagnostics Control Registers ..............................................................................................................106
11.1.1 FG Testpoint Enable Register...................................................................................................106
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