T7503 Dual PCM Codec with Filters
Data Sheet
February 1998
Functional Description
The T7503 has one frame sync (FS) input that determines transmit and receive data timing for both channels. The
width of the FS pulse determines the order of the two channels on the PCM buses. If FS is nominally one MCLK
period wide (see Figure 5), the data for channel 0 is first. If FS is nominally two or more MCLK periods wide (Figure
6), the data for channel 1 is first. During a single 125
µ
s frame, the frame sync input is supplied a single pulse.
The frequency of the master clock must be either 2.048 MHz or 4.096 MHz. Internal circuitry determines the
master clock frequency during the powerup reset interval.
Powerdown is achieved by removing the FS pulse for at least 500
µ
s with MCLK active, after which MCLK may be
removed. Both channels are powered down together. Powerdown is not guaranteed if MCLK is lost, unless the
device is already in the powerdown mode.
R
FN
R
IN
R
IP
GS
Xn
VF
X
INn
–
VF
X
IPn
VCM0
2.4 V
+
TO
CODEC
FILTERS
R
FP
GAIN =
R
FN
R
IN
5-3787
Figure 2. Typical Analog Input Section
Pin Information
VF
R
OP0
VF
R
ON0
GNDA0
VF
X
IN0
VF
X
IP0
GS
X
0
VCM0
V
DD
MCLK
GNDD
1
2
3
4
5
6
7
8
9
10
T - 7503 - - - EL
20
19
18
17
16
15
14
13
12
11
VF
R
OP1
VF
R
ON1
GNDA1
VF
X
IN1
VF
X
IP1
GS
X
1
VCM1
FS
D
R
D
X
5-3788
Figure 3. Pin Diagram
2
Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
