Data Sheet
February 1998
T7503 Dual PCM Codec with Filters
Pin Information
(continued)
Table 1. Pin Descriptions
Symbol
VF
X
IN1
VF
X
IN0
VF
X
IP1
VF
X
IP0
GS
X
1
GS
X
0
VF
R
OP1
VF
R
OP0
VF
R
ON1
VF
R
ON0
V
DD
Pin
17
4
16
5
15
6
20
1
19
2
8
Type
Name/Function
I
Voice Frequency Transmitter Negative Input.
Analog inverting input to the
uncommitted operational amplifier at the transmit filter input.
I
Voice Frequency Transmitter Positive Input.
Analog noninverting input to the
uncommitted operational amplifier at the transmit filter input.
O
Gain Set for Transmitter.
Output of the transmit uncommitted operational amplifi-
er. The pin is the input to the transmit differential filters.
O
Voice Frequency Receiver Positive Output.
This pin can drive 300
Ω
(or greater)
loads.
O
Voice Frequency Receiver Negative Output.
This pin can drive 300
Ω
(or great-
er) loads.
—
+5 V Power Supply
. This pin should be bypassed to analog ground with at least
0.1
µ
F of capacitance as close to the device as possible. V
DD
serves both analog
and digital internal circuits.
—
Analog Grounds
. Both ground pins must be connected on the circuit board. AGND
serves both analog and digital internal circuits.
I
Receive PCM Data Input
. The data on this pin is shifted into the device on the fall-
ing edges of MCLK. Sixteen consecutive bits of data (8 bits for channel 0, and
8 bits for channel 1) are entered after the FS pulse has been detected.
O
Transmit PCM Data Output
. This pin remains in the high-impedance state except
during active transmit time slots. Sixteen consecutive bits of data (8 bits for channel
0 and 8 bits for channel 1) are shifted out on the rising edge of MCLK. Data is shift-
ed out on the rising edge of MCLK.
I
Master Clock Input
. The frequency must be 2.048 MHz or 4.096 MHz. This clock
serves as the bit clock for all PCM data transfer. A 40% to 60% duty cycle is re-
quired.
—
Digital Ground
. Ground connection for the digital circuitry.
Frame Sync
. This signal is an edge trigger and must be high for a minimum of one
I
d
*
MCLK cycle. This signal must be derived from MCLK. If FS is low for 500
µ
s while
MCLK remains active, then the device fully powers down. An internal pull-down de-
vice is included on FS.
O
Voltage Common Mode
. 2.4 Vdc.
GNDA1
GNDA0
D
R
18
3
12
D
X
11
MCLK
9
GNDD
FS
10
13
VCM0
VCM1
7
14
* I
d
indicates a pull-down device is included on this lead.
Lucent Technologies Inc.
3
AGERE [ AGERE SYSTEMS ]
