T8301 Internet Protocol Telephone
Phone-On-A-Chip
Advance Data Sheet
December 2000
IP Solution DSP
(continued)
4 DSP1600 Core
4.10 Y Space Memory Map
The table below shows the Y space memory map. This is the area can be addressed via the DSP1627’s R0, R1,
R2, and R3 registers, and also by direct (Y-based) addressing.
Table 6. Data Memory Area: I/O, Register, and Memory
Address
R/W
DSP CS
Function
Description
Size
(words)
0x0:0x17FF
0x4000
R/W
R/W
Internal
I/O
Internal RAM
aioc_reg
—
6K
1
Analog audio I/O control register,
see Table 11.
0x4001
0x4002
0x4003
R/W
R/W
R/W
I/O
I/O
I/O
act1_reg
act2_reg
aclkc_reg
Audio codec test register 1.
Audio codec test register 2.
1
1
1
Audio codec clock control register,
see Table 12.
0x4008
0x4010
0x4014
R/W
R/W
R/W
I/O
I/O
I/O
trc_reg
Tone ringer control register, see Table 8.
DMA control register, see Table 14.
1
1
1
dmac_reg
AINsetadr_reg Audio in DMA starting address register,
see Table 15.
0x4015
0x4016
0x4017
0x4018
0x4019
0x401A
Ox401B
0x401C
0x401D
0x401E
0x401F
0x4040
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AINsetcnt_reg Audio in DMA transfer count registers,
see Table 16.
1
1
1
1
1
1
1
1
1
1
1
1
AINadrinc_reg Audio in DMA address increment registers,
see Table 17.
AINcntdec_reg Audio in DMA transfer count decrement regis-
ter, see Table 18.
HNDsetadr_reg Handset DMA starting address register,
see Table 15.
HNDsetcnt_reg Handset DMA transfer count register,
see Table 16.
HNDadrinc_reg Handset DMA address increment register,
(see Table 17).
HNDcntdec_reg Handset DMA transfer count decrement
register, see Table 18.
SPKsetadr_reg Speaker DMA starting address register,
see Table 15.
SPKsetcnt_reg Speaker DMA transfer count register,
see Table 16.
SPKadrinc_reg Speaker DMA address increment register,
see Table 17.
SPKcntdec_reg Speaker DMA transfer count decrement
register, see Table 18.
config_compander Compander configuration register,
see Table 19.
0x4041
0x4041
0x4042
W
R
I/O
I/O
I/O
write_companded Write companded value register, see Table 21.
1
1
1
read_linear
write_linear
Read linear value register, see Table 22.
Write linear value register, see Table 20.
W
Lucent Technologies Inc.
15
AGERE [ AGERE SYSTEMS ]
