T8301 Internet Protocol Telephone
Phone-On-A-Chip
IP Solution DSP
Advance Data Sheet
December 2000
4 DSP1600 Core
(continued)
s
Dual-port (core) RAM, DPRAM—6K x 16:
— This block is a true dual-port memory and is accessible simultaneously by both the X and Y bus system. Two
locations can be
either
read
or
written in the same instruction execution. This memory block resides at loca-
tions 0x0000—0x17FF on both the X and Y maps. This block will operate with zero wait states. The DPRAM
contains 6K x 16-bit words of zero wait-state memory, which is organized into six banks of 1K x 16-bit words.
Each bank has separate ports to the instruction/coefficient and data memory spaces. Dual accesses to both
memory spaces in separate banks incur no wait-states; however, accesses to the same bank from both
spaces will add one wait-state to the total access time.
Internal SRAM, ISRAM—16K x 16:
— Although this is a dual-port RAM, there is only one bus system to the RAM itself. The X and Y bus is multi-
plexed before the RAM and is actually addressed via the external memory interface (EMI). Two locations can
be
either
read
or
written in the same instruction execution, but will require two clock cycles. The X memory
location is at 0xC000—0xFFFF and the Y memory location is at 0x8000—0xBFFF, and also at 0xC000—
0xFFFF. (Referred to as mirrored. A write to 0x8000 on the Y map will also write to 0xC000). There is only one
block of 16K; however, it appears twice on the Y map.
There is one wait-state required for both the X and
Y bus to access this RAM.
External SRAM, XSRAM—12K x 16:
— Responds only to the Y data bus. The T8301 generates a chip select called X_CSN (active-low), pin 43. It
uses the EMI to generate the address and data.
There is one wait-state required for both the X and Y bus
to access this RAM.
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Lucent Technologies Inc.
AGERE [ AGERE SYSTEMS ]
