Data Sheet
June 2003
TTSV02622 STS-24 Backplane Transceiver
Timing Characteristics
(continued)
CPU Interface Timing
T
ACCESS_MIN
T
PULSE
CS_N
T
RD_WR_N, ADDR_MAX, DB_HOLD
RD_WR_N
ADDR[6:0]
DB[7:0]
INTERNAL REGISTER
(SYS_CLK
DOMAIN)
T
ADDR_MAX
T
DAT_MAX,
T
RD_WR_MAX
T
WRITE_MAX
INT_N
DATA VALID
OLD VALUE
NEW VALUE
T
INT_MAX
Figure 20. Write Transaction
Table 26. Write Transaction Timing Requirements
Symbol
T
PULSE
T
ADDR_MAX
T
DAT_MAX
T
RD_WR_MAX
T
WRITE_MAX
T
ACCESS_MIN
Parameter
Minimum Pulse Width for CS_N
Maximum Time from Negative Edge of CS_N to ADDR Valid
Maximum Time from Negative Edge of CS_N to Data Valid
Maximum Time from Negative Edge of CS_N to Negative
Edge of RD_WR_N
Maximum Time from Negative Edge of CS_N to Contents of
Internal Register Latching DB[7:0]
Minimum Time Between a Write Cycle (falling edge of
CS_N) and Any other Transaction (read or write, at falling
edge of CS_N)
Maximum Time from Register FF to Pad
Minimum Hold Time that RD_WR_N, ADDR, and DB Must
Be Held Valid from the Negative Edge of CS_N
Min
5
—
—
—
—
60
Max
—
18
25
26
60
—
Unit
ns
ns
ns
ns
ns
ns
T
INT_MAX
T
RD_WR_N
,
ADDR_MAX
,
DB_HOLD
—
57
20
—
ns
ns
Agere Systems Inc.
61
AGERE [ AGERE SYSTEMS ]
