TTSV02622 STS-24 Backplane Transceiver
Data Sheet
June 2003
Timing Characteristics
(continued)
CPU Interface Timing
(continued)
T
ACCESS_MIN
T
PULSE
CS_N
T
DH
RD_WR_N
ADDR[6:0]
T
HIZ_MAX
DB[7:0]
DATA VALID
T
ADDR_MAX
T
RD_WR_MAX
T
DATA_MAX
Figure 21. Read Transaction
Table 27. Read Transaction Timing Requirements
Symbol
T
PULSE
T
ADDR_MAX
T
RD_WR_MAX
T
DATA_MAX
T
HIZ_MAX
T
DH
T
ACCESS_MIN
Parameter
Minimum Pulse Width for CS_N
Maximum Time from Negative Edge of CS_N to Addr Valid
Maximum Time from Negative Edge of CS_N to RD_WR_N Rising
Maximum Time from Negative Edge of CS_N to Data Valid on DB Port
Maximum Time from Rising Edge of CS_N to DB Port Going HI-Z
Data Hold Time After CS_N Is Deasserted
Minimum Time Between a Read Cycle (falling edge of CS_N) and Any
Other Transaction (read or write, at falling edge of CS_N)
Min
5
—
—
—
—
0
60
Max
—
5
5
56
12
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
62
Agere Systems Inc.
AGERE [ AGERE SYSTEMS ]
