Switching Characteristics
Table 5. Switching Characteristics
Min/Max specifications at V
DD
= 5.0
±
5%, T
A
= -40 to + 85°C.
Symbol Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
t
CLK
t
CHH
t
CD[1]
t
ODE
t
ODZ
t
SDV
t
CLH
t
SS[2]
t
OS[2]
t
SH[2]
t
OH[2]
t
RST
t
DCD
t
DSD
t
DOD
t
UDD
t
CHD
t
CLD
t
UDH
t
UDCS
t
UDCH
Clock period
Pulse width, clock high
Delay time, rising edge of clock to valid, updated count
information on D0-7
Delay time, OE fall to valid data
Delay time, OE rise to Hi-Z state on D0-7
Delay time, SEL valid to stable, selected data byte
(delay to High Byte = delay to Low Byte)
Pulse width, clock low
Setup time, SEL before clock fall
Setup time, OE before clock fall
Hold time, SEL after clock fall
Hold time, OE after clock fall
Pulse width, RST low
Hold time, last position count stable on D0-7 after clock rise
Hold time, last data byte stable after next SEL state change
Hold time, data byte stable after OE rise
Delay time, U/D valid after clock rise
Delay time, CNT
DCDR
or CNT
CAS
high after clock rise
Delay time, CNT
DCDR
or CNT
CAS
low after clock fall
Hold time, U/D stable after clock rise
Setup time, U/D valid before CNT
DCDR
or CNT
CAS
rise
Hold time, U/D stable after CNT
DCDR
or CNT
CAS
rise
10
t
CLK
-45
t
CLK
-45
28
20
20
0
0
28
10
5
5
45
45
45
Min.
70
28
65
65
40
65
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. t
CD
specification and waveform assume latch not inhibited.
2. t
SS
, t
OS
, t
SH
, t
OH
only pertain to proper operation of the inhibit logic. In other cases, such as 8 bit read operations, these setup
and hold times do not need to be observed.
Figure 3. Tri-State Output Timing.
2-182
AGILENT [ AGILENT TECHNOLOGIES, LTD. ]
