AK4430 参数 Datasheet PDF下载

[AK4430]

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System Reset

The AK4430 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up.

The AK4430 is in power-down mode until LRCK are input.

Power Supply

(VDD, CVDD)

(5)

MCLK

Low

20 us

Analog

Circuit

Power down

(1)

Power-up

2, 3

LRCK

Digital

Circuit

Power down

(2)

Power-up

Charge Pump

Circuit

Power down

Power-up

(3)

Charge Pump

Counter circuit

Time A

D/A In

(Digital)

D/A Out

(Analog)

“0” data

MUTE (D/A Out)

(4)

Notes:

(1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up.

(2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK.

(3) The charge pump counter starts after the charge pump circuit is powered-up. The DAC outputs a valid analog signal

after Time A.

Time A =176/fs: Normal speed mode

Time A =352/fs: Double speed mode

Time A =704/fs: Quad speed mode

(4) No audible click noise occurs under normal conditions.

(5) The power supply must be powered-up when the MCLK pin is “L”. MCLK must be input after 20us when the power

supply voltage achieves 80% of VDD. If not, click noise may occur at different time from this figure.

Figure 8. System Reset Diagram

MS1196-E-01

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2011/03