[AK4430]
OPERATION OVERVIEW
■
System Clock
The external clocks required to operate the AK4430 are MCLK, LRCK, and BICK. The master clock (MCLK) should be
synchronized with LRCK, but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically, and then the internal master
clock is set to the appropriate frequency (Table
1).
The AK4430 is automatically placed in power saving mode when MCLK, LRCK and BICK stop during normal operation
mode, and the analog output goes to 0V(typ). When MCLK, LRCK and BICK are input again, the AK4430 is powered
up. After exiting reset following power-up, the AK4430 is not fully operational until MCLK, LRCK and BICK are input.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
384fs
512fs
-
16.3840
-
22.5792
-
24.5760
12.288
16.9344
18.432
33.8688
-
36.8640
-
-
-
-
-
Sampling
Speed
Normal
128fs
-
-
-
192fs
-
-
-
-
-
22.5792
24.5760
-
-
33.8688
36.8640
256fs
-
-
-
8.192
11.2896
12.288
22.5792
24.5760
-
-
768fs
24.5760
33.8688
36.8640
1152fs
36.8640
-
-
Double
-
-
-
-
-
-
-
-
Quad
Table 1. System Clock Example
When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table
1).
However, when
the sampling rate is 32kHz~48kHz, DR and S/N will degrade as compared to when MCLK= 512fs/768fs (Table
2).
MCLK
DR,S/N
256fs/384fs
101dB
512fs/768fs
104dB
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
■
Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The AK4430 supports two formats as
shown in
The serial data is MSB-first, two’s complement format and it is latched on the rising edge of BICK. It
can be used for 16/20 bit I
2
S formats by zeroing the unused LSBs.
Mode
0
1
DIF pin
L
H
SDTI Format
24bit MSB justified
24bit I
2
S
Table 3. Audio Data Format
BICK
≥48fs
≥48fs
Figure
MS1196-E-01
-9-
2011/03