3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
Terminal List
LB
Terminal Name
CP
CP
1
& CP
2
NC
PHASE
ROSC
GROUND
LOGIC SUPPLY
ENABLE
NC
PFD
2
BLANK
PFD
1
REF
EXT MODE
NO CONNECT
OUT
A
NC
SENSE
NC
GROUND
LOAD SUPPLY
OUT
B
NO CONNECT
SLEEP
V
REG
GROUND
Terminal Description
Reservoir capacitor (typically 0.22
µF)
The charge pump capacitor (typically 0.22
µF)
No (internal) connection
Logic input for direction control
Oscillator resistor
Grounds
V
DD
, the low voltage (typically 5 V) supply
Logic input for enable control
No (internal) connection
Logic-level input for fast decay
Logic-level input for blanking control
Logic-level input for fast decay
V
REF
, the load current reference input voltage
Logic input for PWM mode control
No (Internal) connection
One of two DMOS bridge outputs to the motor
No (internal) connection
Sense resistor
No (internal) connection
Grounds
V
BB
, the high-current, 9.5 V to 50 V, motor supply
One of two DMOS bridge outputs to the motor
No (Internal) connection
Logic-level Input for sleep operation
Regulator decoupling capacitor (typically 0.22
µF)
Ground
(SOIC)
1
2&3
—
4
B
(DIP)
24
1&2
—
3
LP
(TSSOP)
1
2&3
4
5
6
7, 8*
9
10
11
12
13
14
15
16
17
18
19, 20
21
22
—
23
24
25
26
27
28*
5
4
6, 7 5, 6, 7, 8*
8
9
–
10
11
12
13
14
15
16
–
17
–
9
10
–
11
12
13
14
15
—
16
–
17
–
18, 19 18, 19*
20
20
21
22
23
24
—
21
—
22
23
—
* For the A3959SB (DIP) only, there is an indeterminate resistance between the substrate grounds (pins 6, 7,
18, and 19) and the grounds at pins 5 and 8. Pins 5 and 8, and 6, 7, 18, or 19 must be connected together
externally. For the A3959SLP (TSSOP) the grounds at terminals 7, 8, and 28 should be connected together at
the exposed pad beneath the device.
8
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
