5890 AND 5891
8-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
CLOCK
A
D
B
DATA IN
STROBE
BLANKING
OUTN
E
F
C
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the OUTPUT ENABLE input be high
during serial data entry.
G
Dwg. No. A-12,649A
TIMING REQUIREMENTS
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
When the OUTPUT ENABLE input is high,
all of the output buffers are disabled (off) without
affecting the information stored in the latches or
shift register. With the OUTPUT ENABLE input
low, the outputs are controlled by the state of
their respective latches.
(Data Set-Up Time).......................................................................... 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) ............................................................................. 75 ns
C. Minimum Data Pulse Width ................................................................ 150 ns
D. Minimum Clock Pulse Width............................................................... 150 ns
E. Minimum Time Between Clock Activation and Strobe ....................... 300 ns
F. Minimum Strobe Pulse Width ............................................................. 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion ......................................................................... 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
TRUTH TABLE
Serial
Data Clock
Input Input I
Shift Register Contents
Serial
Data Strobe
Output Input
Latch Contents
...
Output Contents
... I
Output
Enable
I
I
...
I
I
I
I
I
I
I
I
I
I
I
N-1 N
1
2
3
N-1
N
1
2
3
N-1
N
1
2
3
H
L
H
L
R1 R2 ... RN-2 RN-1
R1 R2 ... RN-2 RN-1
RN-1
RN-1
RN
X
R1 R2 R3 ... RN-1 RN
...
P1 P2 P3 ... PN-1 PN
X
X
X
X
X
X
X
L
R1 R2 R3 ... RN-1 RN
P1 P2 P3 ... PN-1 PN
PN
X
H
X
L
L
P1 P2 P3 ... PN-1 PN
... L
...
X
X
H
L
L
L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
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Worcester, Massachusetts 01615-0036 (508) 853-5000
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
