May 2001
Preliminary
®
3.3V 2M
×
8/1M
×
16 CMOS synchronous DRAM
Features
• Organization
- 1,048,576 words × 8 bits × 2 banks (2M × 8)
11 row, 9 column address
- 524,288 words × 16 bits × 2 banks (1M × 16)
11 row, 8 column address
AS4LC2M8S1
AS4LC2M8S0
AS4LC1M16S1
AS4LC1M16S0
• All signals referenced to positive edge of clock, fully
synchronous
• Dual internal banks controlled by A11 (bank select)
• High speed
- 143/125/100 MHz
- 7/8/10 ns clock access time
• Auto refresh and self refresh
• PC100 functionality
• Automatic and direct precharge including concurrent
autoprecharge
• Burst read, write/Single write
• Random column address assertion in every cycle, pipelined
operation
• LVTTL compatible I/O
• 3.3V power supply
• JEDEC standard package, pinout and function
- 400 mil, 44-pin TSOP 2 (2M × 8)
- 400 mil, 50-pin TSOP 2 (1M × 16)
• Low power consumption
- Active: 576 mW max
- Standby: 7.2 mW max, CMOS I/O
• 2048 refresh cycles, 32 ms refresh interval
• 4096 refresh cycles, 64 ms refresh interval
• Read/write data masking
• Programmable burst length (1/2/4/8/ full page)
• Programmable burst sequence (sequential/interleaved)
• Programmable CAS latency (1/2/3)
Pin arrangement
TSOP 2
V
CC
DQ0
V
SSQ
DQ1
V
CCQ
DQ2
V
SSQ
DQ3
V
CCQ
NC
NC
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
SS
DQ7
V
SSQ
DQ6
V
CCQ
DQ5
V
SSQ
DQ4
V
CCQ
NC
NC
DQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
CCQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
CCQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TSOP 2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
CCQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
CCQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
Pin designation
Pin(s)
DQM (2M × 8)
UDQM/LDQM (1M × 16)
A0 to A10
A11
DQ0 to DQ7 (2M
×
8)
DQ0 to DQ15 (1M
×
16)
RAS
CAS
WE
CS
V
CC
, V
CCQ
V
SS
, V
SSQ
CLK
CKE
Description
Output disable/write mask
RA0 – 10
Address inputs CA0 – 7 (×16)
CA0 – 8 (×8)
Bank address (BA)
Input/output
Row address strobe
Column address strobe
Write enable
Chip select
Power (3.3V ± 0.3V)
Ground
Clock input
Clock enable
AS4LC2M8S1
and
AS4LC2M8S0
LEGEND
Configuration
Refresh Count
Row Address
Bank Address
Column Address
2M
×
8
1M
×
8
×
2 banks
2K/4K
(A0 – A10)
2 (BA)
512 (A0 – A8)
Selection guide
Symbol
Bus frequency (CL = 3)
Maximum clock access time (CL = 3)
Minimum input setup time
Minimum input hold time
Row cycle time (CL = 3, BL = 1)
Maximum operating current ([×16], RD or
WR, CL = 3), BL = 2
Maximum CMOS standby current, self refresh
5/21/01; v.1.1
AS4LC1M16S0
and
AS4LC1M16S1
1M
×
16
512K
×
16
×
2 banks
2K/4K
(A0 – A10)
2 (BA)
256 (A0 – A7)
–7
143
5.5
2
1.0
70
130
1
–8
125
6
2
1.0
80
100
1
–10
100
6
2
1.0
80
100
1
P. 1 of 29
Unit
MHz
ns
ns
ns
ns
mA
mA
f
Max
t
AC
t
S
t
H
t
RC
I
CC1
I
CC6
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