AS4LC2M8S1
AS4LC1M16S1
®
Sym
t
MRD
t
OH
t
PED
t
RAS
t
RC
t
RCAR
t
RCD
t
REF
t
ROH
t
RP
t
RRD
t
T
t
WR
t
XSR
Parameter
Load mode register to
active/refresh command
Output data hold time @
30 pF
CKE to CLOCK enable or
power-down exit mode
Active to precharge
command
Active command period
Auto refresh period
Active to read or write
delay
Refresh period—2048
rows
Data-out high Z from
precharge/burst stop
command
Precharge command
period
Active Bank A to Active
Bank B command
Transition time
WRITE recovery time
Exit SELF REFRESH to
ACTIVE command
CAS
latency
–7
Min
2
Max
–
–
–
–
–
120,000
–
–
–
64
–
–
–
–
–
1.0
–
–
Min
2
2.5
2.5
2.5
1
48
80
80
3
–
3
2
1
3
16
0.3
2
80
–8
Max
–
–
–
–
–
120,000
–
–
–
64
–
–
–
–
–
1.0
–
–
Min
2
3
3
3
1
50
80
80
3
–
3
2
1
3
20
0.3
2
80
–10
Max
–
–
–
–
–
120,000
–
–
–
64
–
–
–
–
–
1.0
–
–
Unit
t
CK
ns
ns
ns
t
CK
ns
ns
ns
t
CK
ms
t
CK
t
CK
t
CK
t
CK
ns
ns
t
CK
ns
20
9
9
9
8
8
Notes
5
6
6
6
3
2
1
2
2
2
1
42
70
70
3
3
–
8
3
2
1
3
3
2
1
3
14
0.3
2
70
Notes
1 I
DD
is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.
2 Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid V
IH
or V
IL
levels.
3 Address transitions average one transition every two-clock period.
4 The I
DD
current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-latency is reduced.
5 t
CK
= 7 ns for –7, 8 ns for –8, and 10 ns for –10.
6 If clock t
r
> 1 ns, (t
r/2
– 0.5)ns should be added to the parameter.
7 If clock (t
r
and t
f
) > 1 ns, [(t
r
+ t
f
)/2 – 1] ns should be added to the parameter.
8 V
IH
overshoot: V
IH(max)
= V
DDQ
+ 2V for a pulse width
≤
3 ns, and the pulse width cannot be greater than one third of the cycle rate. V
IL
undershoot:
V
IL(min)
= –2V for a pulse width
≤
3 ns and the pulse width cannot be greater than one third of the cycle rate.
9 Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter.
10 The clock frequency must remain constant during access or precharge states (READ, WRITE, including t
WR
and PRECHARGE commands). CKE may be
used to reduce the data rate.
11 Timing actually specified t
WR
plus t
RP
; clock(s) specified as a reference only at minimum cycle rate.
12 Timing actually specified by t
WR
.
13 t
HZ
defines the time at which the output achieves the open circuit condition; it is not a reference to V
OH
or V
OL
. The last valid data element will meet t
OH
before going to HIGH-Z.
14 CLK must be toggled a minimum of two times during this period.
15 Enables on-chip refresh and address counters.
16 All voltages referenced to V
SS
.
17 The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0° C
≤
T
A
≤
70° C) is
endured.
5/21/01; v.1.1
Alliance Semiconductor
P. 9 of 29
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
