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AS7C1024-15JI 参数 Datasheet PDF下载

AS7C1024-15JI图片预览
型号: AS7C1024-15JI
PDF下载: 下载PDF文件 查看货源
内容描述: 5V / 3.3V 128K ×8 CMOS SRAM (进化引脚) [5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 9 页 / 199 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS7C1024
AS7C31024
®
Read cycle (over the operating range)
-10
Parameter
Read cycle time
Address access time
Chip enable (CE1) access time
Chip enable (CE2) access time
Output enable (OE) access time
Output hold from address change
CE1 Low to output in low Z
CE2 High to output in low Z
CE1 Low to output in high Z
CE2 Low to output in high Z
OE Low to output in low Z
OE High to output in high Z
Power up time
Power down time
Symbol
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
OH
t
CLZ1
t
CLZ2
t
CHZ1
t
CHZ2
t
OLZ
t
OHZ
t
PU
t
PD
Min
10
2
3
3
0
0
Max
10
10
10
3
3
3
3
10
12
3
3
3
0
0
-12
Min
Max
12
12
12
3
3
3
3
12
15
3
3
3
0
0
-15
Min
Max
15
15
15
4
4
4
4
15
20
3
3
3
0
0
-20
Min
Max
20
20
20
5
5
5
5
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5, 12
4, 5, 12
4, 5, 12
4, 5, 12
4, 5
4, 5
4, 5, 12
4, 5, 12
3
3, 12
3, 12
Notes
Key to switching waveforms
Rising input
Falling input
Undefined / don’t care
Read waveform 1 (address controlled)
t
RC
Address
D
OUT
t
AA
Data valid
t
OH
Read waveform 2 (CE1, CE2, and OE controlled)
CE1
CE2
OE
D
OUT
Current
supply
t
ACE1
,
tACE2
t
CLZ1
, t
CLZ2
t
PU
Data valid
t
PD
50%
50%
I
CC
I
SB
t
OE
t
OLZ
t
OHZ
t
CHZ1
, t
CHZ2
t
RC1
4
ALLIANCE SEMICONDUCTOR
11/29/00