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AS7C1024-15JI 参数 Datasheet PDF下载

AS7C1024-15JI图片预览
型号: AS7C1024-15JI
PDF下载: 下载PDF文件 查看货源
内容描述: 5V / 3.3V 128K ×8 CMOS SRAM (进化引脚) [5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 9 页 / 199 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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®
AS7C1024
AS7C31024
Write cycle (over the operating range)
-10
Parameter
Write cycle time
Chip enable (CE1) to write end
Chip enable (CE2) to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Shaded areas contain advance information.
-12
Min
12
10
10
10
0
8
0
6
0
3
Max
5
5
15
12
12
12
0
9
0
9
0
3
-15
Min
Max
5
20
12
12
12
0
12
0
10
0
3
-20
Min
Max
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4, 5
4, 5
4, 5
12
12
12
Notes
Symbol
t
WC
t
CW1
t
CW2
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Min
10
9
9
9
0
7
0
6
0
3
Max
Write waveform 1 ( WE controlled)
t
AW
Address
t
WP
WE
t
AS
D
IN
t
WZ
D
OUT
t
DW
Data valid
t
OW
t
DH
t
WC
t
AH
Write waveform 2 (CE1 and CE2 controlled)
t
AW
Address
t
AS
CE1
CE2
WE
t
WZ
D
IN
D
OUT
t
WP
t
DW
Data valid
t
DH
t
CW1
, t
CW2
t
WC
t
AH
11/29/00
ALLIANCE SEMICONDUCTOR
5